Pixel circuit, light emitting display device, and driving method thereof

Patent metadata

Field	Value
Publication number	US-11335247-B2
Application number	US-202017121059-A
Country	US
Kind code	B2
Filing date	Dec 14, 2020
Priority date	Dec 30, 2019
Publication date	May 17, 2022
Grant date	May 17, 2022

Abstract

A light emitting display device includes a pixel circuit including: a first transistor having a first electrode connected to a first node coupled to a first power supply line, a second electrode connected to a second node, and a gate electrode connected to a third node; a second transistor having a first electrode connected to the first node, a second electrode connected to the third node, and a gate electrode connected to a first gate line; a light emitting diode connected to the first transistor; a first capacitor having a first electrode connected to the third node and a second electrode connected to a conductive line and an anode electrode of the light emitting diode; and a second capacitor having a first electrode connected to the third node and a second electrode connected to a constant voltage source which supplies a DC voltage.

First claim

What is claimed is:

1. A pixel circuit comprising:
a first transistor having:
a first electrode connected to a first node which is coupled to a first power supply line supplying a first source voltage,
a second electrode connected to a second node, and
a gate electrode connected to a third node;

a second transistor having:
a first electrode directly connected to the first node,
a second electrode connected to the third node, and
a gate electrode connected to a first gate line;

a light emitting diode coupled to the first transistor;
a first capacitor having:
a first electrode connected to the third node, and
a second electrode connected to a conductive line and an anode electrode of the light emitting diode, the conductive line coupled to a second power supply line supplying an initialization voltage; and

a second capacitor having:
a first electrode connected to the third node, and

a second electrode connected to a constant voltage source which supplies a DC voltage.

2. The pixel circuit according to claim 1 , wherein the second transistor includes an oxide semiconductor.

3. The pixel circuit according to claim 1 , wherein the second electrode of the second capacitor is connected to the first power supply line supplying the first source voltage.

4. The pixel circuit according to claim 1 , wherein the second capacitor prevents a voltage of the third node from fluctuating due to a kickback phenomenon which occurs when the second transistor is turned on or turned off.

5. The pixel circuit according to claim 1 , further comprising:
a third transistor having:
a first electrode connected to the second node,
a second electrode is connected to a data line, and
a gate electrode connected to a second gate line;

a fourth transistor having:
a first electrode connected to the second node,
a second electrode connected to the light emitting diode, and
a gate electrode connected to a first emission line;

a fifth transistor having:
a first electrode supplied with the first source voltage,
a second electrode connected to the first node, and
a gate electrode connected to a second emission line; and

a sixth transistor having:
a first electrode supplied with the initialization voltage,
a second electrode connected to the conductive line, and
a gate electrode connected to the first gate line.

6. The pixel circuit according to claim 5 , wherein the pixel circuit operates separately in:
an initialization period in which the fifth transistor is switched to an ON state, then the second transistor and the sixth transistor are switched to an ON state, and the third transistor and the fourth transistor are maintained in an OFF state;
a writing period in which the second transistor, the sixth transistor and the fifth transistor are switched to the OFF state, the third transistor is switched to the ON state, and the fourth transistor is maintained in the OFF state;
a sampling period in which the second transistor and the sixth transistor are switched to the ON state, the third transistor is maintained in the ON state, and the fourth transistor and the fifth transistor are maintained in the OFF state; and
an emission period in which the second transistor, the sixth transistor, and the third transistor are switched to the OFF state and then the fourth transistor and the fifth transistor are sequentially switched to the ON state.

7. The pixel circuit according to claim 6 ,
wherein, in the initialization period, a voltage corresponding to the first source voltage is stored in the third node by the first capacitor, and
wherein, in the sampling period, a voltage corresponding to a data signal supplied by the data line and a voltage corresponding to a threshold voltage of first transistor are stored in the third node by the first capacitor.

8. A light emitting display device comprising:
a display panel that includes a plurality of data lines, a plurality of gate lines, a plurality of emission lines, and a plurality of pixels which are connected to the plurality of data lines, the plurality of gate lines, and the plurality of emission lines;
a data driver that supplies a data signal to the plurality of data lines;
a gate driver that supplies a gate signal to the plurality of gate lines and supplies an emission signal to the plurality of emission lines; and
a timing controller that controls the data driver and the gate driver,
wherein each pixel includes:
a first transistor having:
a first electrode connected to a first node which is coupled to a first power supply line supplying a first source voltage,
a second electrode connected to a second node, and
a gate electrode connected to a third node,

a second transistor having:
a first electrode directly connected to the first node,
a second electrode connected to the third node, and
a gate electrode connected to a first gate line,

a light emitting diode coupled to the first transistor,
a first capacitor having:
a first electrode connected to the third node, and
a second electrode connected to a conductive line and an anode electrode of the light emitting diode, the conductive line coupled to a second power supply line supplying an initialization voltage, and

a second capacitor having:
a first electrode connected to the third node, and
a second electrode connected to a constant voltage source which supplies a DC voltage.

9. The light emitting display device according to claim 8 , wherein the second transistor includes an oxide semiconductor.

10. The light emitting display device according to claim 8 , wherein the second electrode of the second capacitor is connected to the first power supply line supplying the first source voltage.

11. The light emitting display device according to claim 8 , wherein the second capacitor prevents a voltage of the third node from fluctuating due to a kickback phenomenon which occurs when the second transistor is turned on or turned off.

12. The light emitting display device according to claim 8 , wherein each pixel further includes:
a third transistor having:
a first electrode connected to the second node,
a second electrode connected to the data line, and
a gate electrode connected to a second gate line;

a fourth transistor having:
a first electrode connected to the second node,
a second electrode connected to the light emitting diode, and
a gate electrode connected to a first emission line;

a fifth transistor having:
a first electrode supplied with the first source voltage,
a second electrode connected to the first node, and
a gate electrode connected to a second emission line; and

a sixth transistor having:
a first electrode supplied with the initialization voltage,
a second electrode connected to the conductive line, and a gate electrode is connected to the first gate line.

13. The light emitting display device according to claim 12 , wherein each pixel operates separately in:
an initialization period in which the fifth transistor is switched to an ON state, then the second transistor and the sixth transistor are switched to an ON state, and the third transistor and the fourth transistor are maintained in an OFF state;
a writing period in which the second transistor, the sixth transistor and the fifth transistor are switched to the OFF state, the third transistor is switched to the ON state, and the fourth transistor is maintained in the OFF state;
a sampling period in which the second transistor and the sixth transistor are switched to the ON state, the third transistor is maintained in the ON state, and the fourth transistor and the fifth transistor are maintained in the OFF s

Assignees

• Lg Display Co Ltd

Inventors

• Bong Junho
• Park Minwoo

Classifications

• H10D86/481

  integrated with passive devices, e.g. auxiliary capacitors · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/423

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D30/6755

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title