Organic light-emitting diode (oled) display

Patent metadata

Field	Value
Publication number	US-2016233281-A1
Application number	US-201514833345-A
Country	US
Kind code	A1
Filing date	Aug 24, 2015
Priority date	Feb 10, 2015
Publication date	Aug 11, 2016
Grant date	—

Abstract

An organic light-emitting diode (OLED) display is disclosed. In one aspect, the OLED display includes a substrate and an active pattern formed over the substrate. The OLED display also includes first and second gate electrodes formed over the active pattern. The first gate electrode defines a first transistor together with the active pattern. The second gate electrode defines a second transistor and a third transistor together with the active pattern. The OLED display further includes a first conductive pattern formed over the first and second gate electrodes. The first conductive pattern overlaps at least a portion of the second and/or third transistors so as to define a parasitic capacitor.

First claim

What is claimed is:

1 . An organic light-emitting diode (OLED) display, comprising:
a substrate; an active pattern formed over the substrate and including: a first region, a second region, a third region, a fourth region, a fifth region, and a sixth region, wherein the second region and the sixth region are electrically connected to each other, and wherein the fourth region and the fifth region are electrically connected to each other; a gate insulation layer formed over the active pattern; a first gate electrode formed over the gate insulation layer, wherein the first gate electrode defines a first transistor together with the first region and the second region; a second gate electrode formed on the same layer as the first gate electrode, wherein the second gate electrode defines: i) a second transistor together with the third region and the fourth region which are arranged in a first direction ii) a third transistor together with the fifth region and the sixth region which are arranged in a second direction, wherein the second direction is substantially perpendicular to the first direction; a first insulating interlayer formed over the first gate electrode, the second gate electrode, and the gate insulation layer; a first conductive pattern formed over the first insulating interlayer, wherein the first conductive pattern overlaps at least a portion the fourth and fifth regions, wherein the first conductive pattern defines a parasitic capacitor together with the portion the fourth and fifth regions; and an OLED configured to receive a driving current from the first transistor, wherein the second and third transistors are configured to provide an initialization voltage to the first transistor.

2 . The OLED display of claim 1 , wherein the second gate electrode includes:
a second gate extended portion extending in the first direction; and a second gate protruding portion protruded from the second gate extended portion in the second direction.

3 . The OLED display of claim 2 , wherein a first portion of the second gate extended portion is configured to serve as a gate electrode of the third transistor, and wherein a first portion of the second gate protruding portion is configured to serve as a gate electrode of the second transistor.

4 . The OLED display of claim 1 , wherein the second and third transistor are electrically connected in series and configured to serve as a dual gate transistor.

5 . The OLED display of claim 3 , wherein the active pattern further includes a seventh region and an eighth region, wherein the second gate electrode defines a fourth transistor together with the seventh region and the eighth region, wherein a second portion that opposes the first portion of the second gate extended portion is configured to serve as a gate electrode of the fourth transistor, and wherein the eighth region is electrically connected to the first region.

6 . The OLED display of claim 1 , further comprising a second conductive pattern formed on the same layer the first conductive pattern, wherein the second conductive pattern overlaps the first gate electrode and the first and second regions of the active pattern, wherein the second conductive pattern defines an opening that exposes at least a portion the first conductive pattern, and wherein the second conductive pattern defines a storage capacitor together with the first gate electrode.

7 . The OLED display of claim 6 , wherein the second conductive pattern and the first conductive pattern are simultaneously formed using the same materials.

8 . The OLED display of claim 1 , further comprising a second insulating interlayer formed over the first conductive pattern and the first insulating interlayer.

9 . The OLED display of claim 8 , further comprising a first connection pattern formed over the second insulating interlayer, wherein the first connection pattern is configured to apply the initialization voltage to the first conductive pattern.

10 . The OLED display of claim 9 , wherein the first connection pattern fills a first contact hole, and wherein the first connection pattern is electrically connected to the first conductive pattern via the first contact hole.

11 . The OLED display of claim 10 , wherein the active pattern further includes a ninth region, a tenth region, an eleventh region, a twelfth region, a thirteenth region, a fourteenth region, a fifteenth region, a sixteenth region, a seventeenth region, and an eighteenth region.

12 . The OLED display of claim 11 , further comprising:
a third gate electrode formed over the gate insulation layer, wherein the third gate electrode defines: i) a fifth transistor together with the ninth region and the tenth region, ii) a sixth transistor together with the eleventh region and the twelfth region, and iii) a seventh transistor together with the thirteenth region and the fourteenth region; and a fourth gate electrode formed on the same layer as the third gate electrode, wherein the fourth gate electrode defines: i) an eighth transistor together with the fifteenth region and a sixteenth region and ii) a ninth transistor together with the seventeenth region and the eighteenth region.

13 . The OLED display of claim 12 , wherein the ninth region is electrically connected to the eleventh region, wherein the tenth region is electrically connected to the third region, wherein the twelfth region is electrically connected to the fourteenth region, wherein the fifteenth region is electrically connected to the second region and the sixth region, and wherein the seventeenth region is electrically connected to the first region and the eighth region.

14 . The OLED display of claim 13 , further comprising a third insulating interlayer formed over the first connection pattern and the second insulating interlayer, wherein the OLED includes:
a first electrode formed over the third insulating interlayer, wherein the first electrode is electrically connected to the thirteenth region or the sixteenth region; an organic light-emitting layer formed over the first electrode; and a second electrode formed over the organic light-emitting layer.

15 . The OLED display of claim 12 , wherein the second gate electrode is configured to receive a scan signal, wherein the third gate electrode is configured to receive a data initialization signal, and wherein the fourth gate electrode is configured to receive an emission signal.

16 . The OLED display of claim 15 , wherein the first conductive pattern is electrically connected to the fourteenth region via the first contact hole, and wherein the twelfth region of the sixth transistor is configured to receive the initialization voltage via the fourteenth region.

17 . The OLED display of claim 16 , further comprising:
a second connection pattern formed over the second insulating interlayer, wherein the second connection pattern is electrically connected to a portion of the third or tenth regions and a portion of the first gate electrode, wherein the second connection pattern fills a second contact hole that is located over the portion of the third or tenth regions and a third contact hole that is located over the portion of the first gate electrode.

18 . The OLED display of claim 17 , further comprising:
a data line formed over the same layer as the second connection pattern, wherein the data line extends in the second direction, and wherein the data line fills a fourth contact hole that is located over the seventh region.

19 . The OLED display of claim 11 , wherei

Assignees

• Samsung Display Co Ltd

Inventors

• Yoon Ju-Won
• Kim Jung-Hwa
• Woo Min-Woo
• Lee Ii-Jeong
• Lee Jeong-Soo

Classifications

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/423

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title

• H10D86/421

  having a particular composition, shape or crystalline structure of the active layer · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title