Neuron circuit

Patent metadata

Field	Value
Publication number	US-11334787-B2
Application number	US-201916509399-A
Country	US
Kind code	B2
Filing date	Jul 11, 2019
Priority date	Jul 12, 2018
Publication date	May 17, 2022
Grant date	May 17, 2022

Abstract

Disclosed is a neuron circuit in which an overflow signal before fire is retained after the fire. The neuron circuit according to an embodiment of the inventive concept includes a synapse element, a synaptic integration unit and a pulse generation unit. The synapse element receives output signals of a pre-neuron circuit and a post-neuron circuit. The synaptic integration unit includes a capacitor charged by the current flowing into the synapse element depending on the output signals of the pre-neuron circuit and the post-neuron circuit. The pulse generation unit generates an output pulse from the charging voltage of the capacitor. The pulse generation unit includes a pulse generation circuit generating the output pulse depending on the charging voltage of the capacitor and an overflow signal retaining unit connected between the capacitor and the pulse generation circuit and retaining an overflow signal, which exceeds a threshold voltage among the charging voltage of the capacitor after the pulse generation unit fires.

First claim

What is claimed is:

1. A neuron circuit comprising:
a synapse element configured to receive output signals of a pre-neuron circuit and a post-neuron circuit, a weight of the synapse element being changed depending on the output signals of the pre-neuron circuit and the post-neuron circuit;
a synaptic integration unit including a capacitor charged by a current flowing through the synapse element depending on the output signals of the pre-neuron circuit and the post-neuron circuit; and
a pulse generation unit configured to generate an output pulse from a charging voltage of the capacitor, the output pulse being fed back to the synapse element as the output signal of the post-neuron circuit,
wherein the pulse generation unit includes:
a pulse generation circuit configured to generate the output pulse depending on the charging voltage of the capacitor; and
an overflow signal retaining unit connected between the capacitor and the pulse generation circuit, the overflow signal retaining unit being configured to retain an overflow signal exceeding a threshold voltage among the charging voltage of the capacitor after the pulse generation unit fires.

2. The neuron circuit of claim 1 , wherein the overflow signal retaining unit is reduced from the charging voltage of the capacitor by the threshold voltage upon firing of the pulse generation unit.

3. The neuron circuit of claim 1 , wherein the overflow signal retaining unit includes:
a first inverter circuit configured to receive the charging voltage of the capacitor; and
a second inverter circuit configured to receive an output signal of the first inverter circuit,
wherein the overflow signal retaining unit is configured to copy the charging voltage of the capacitor to store the copied charging voltage in an output terminal of the second inverter circuit.

4. The neuron circuit of claim 3 , wherein the overflow signal retaining unit further includes a capacitor element connected between the output terminal of the second inverter circuit and a ground.

5. The neuron circuit of claim 3 , wherein the pulse generation circuit includes:
a first transistor having a gate, the charging voltage of the capacitor copied to the output terminal of the second inverter circuit being input to the gate of the first transistor;
a first inverter configured to invert the charging voltage of the capacitor copied to the output terminal of the second inverter circuit and output the inverted charging voltage;
a second inverter configured to invert an output signal of the first inverter and to output the inverted output signal to a drain or a source of the first transistor; and
a second transistor having a gate, an output signal of the second inverter being input to the gate of the second transistor, and the second transistor discharging an output terminal of the second inverter circuit depending on the output signal of the second inverter.

6. The neuron circuit of claim 5 , wherein the pulse generation circuit further includes:
a third transistor having a gate, an output pulse of the second inverter being input to the gate of the third transistor,
wherein one of a drain and a source of the third transistor is connected to a charging terminal of the capacitor and the other is grounded.

7. The neuron circuit of claim 1 , wherein the synapse element includes an excitation synapse element and an inhibition synapse element,
wherein the excitation synapse element includes a first transistor element,
wherein the inhibition synapse element includes a second transistor element,
wherein the output signal of the pre-neuron circuit is input to a first gate of each of the first transistor element and the second transistor element, and
wherein the output signal of the post-neuron circuit is input to a second gate of each of the first transistor element and the second transistor element.

8. The neuron circuit of claim 1 , wherein the synaptic integration unit further includes a current mirror connected between the synapse element and the capacitor,
wherein the current mirror is connected to the excitation synapse element and the inhibition synapse element such that a current constantly flows through the excitation synapse element or the inhibition synapse element depending on the output signals of the pre-neuron circuit and the post-neuron circuit, and outputs a differential current between the excitation synapse element and the inhibition synapse element to the capacitor, and
wherein the capacitor is isolated from the current flowing through the excitation synapse element and the inhibition synapse element by the current mirror and is charged by the differential current.

Assignees

• Seoul Nat Univ R&Db Foundation

Inventors

• Park Byunggook
• Lee Jeong-Jun

Classifications

• H03K3/355 Primary

  Monostable circuits · CPC title

• H03K3/037

  Bistable circuits · CPC title

• G06N3/063 Primary

  using electronic means · CPC title

• G06N3/02

  Neural networks · CPC title