Synapse circuit and neuromorphic system including the same

Patent metadata

Field	Value
Publication number	US-9805302-B2
Application number	US-201414213368-A
Country	US
Kind code	B2
Filing date	Mar 14, 2014
Priority date	May 30, 2013
Publication date	Oct 31, 2017
Grant date	Oct 31, 2017

Abstract

A synapse circuit to perform spike timing dependent plasticity (STDP) operation is provided. The synapse circuit includes a memristor having a resistance value, a transistor connected to the memristor, and the transistor configured to receive at least two input signals. The resistance value of the memristor is changed based on a time difference between the at least two input signals received by the transistor.

First claim

What is claimed is:

1. A synapse circuit to perform spike timing dependent plasticity (STDP) operation, the synapse circuit comprising:
a memristor having a resistance value; and
a transistor connected to the memristor, the transistor configured to receive at least two input signals,
wherein the resistance value of the memristor is changed based on a time difference between the at least two input signals received by the transistor,
wherein terminals of the memristor are respectively coupled to a reference voltage and a drain terminal of the transistor,
wherein the at least two input signals comprise a first input signal applied to a gate terminal of the transistor and a second input signal applied to a source terminal of the transistor, and
wherein the first input signal is provided by a pre-synaptic neuron circuit and the second input signal is provided by a post-synaptic neuron circuit.

2. The synapse circuit of claim 1 , wherein the resistance value of the memristor is changed based on a voltage change caused by the time difference between the at least two input signals.

3. The synapse circuit of claim 1 , wherein the resistance value of the memristor is changed based on a time difference between a first input signal applied to a gate terminal of the transistor and a second input signal based on a membrane voltage applied to a source terminal of the transistor.

4. The synapse circuit of claim 3 , wherein a direction of a current flowing on the memristor is determined by a voltage difference caused by the time difference between the first input signal and the second input signal.

5. The synapse circuit of claim 3 , wherein an amount of a current flowing on the memristor is determined by a voltage difference caused by the time difference between the first input signal and the second input signal.

6. The synapse circuit of claim 3 , wherein the synapse circuit further comprises:
a first terminal connected to the gate terminal of the transistor and configured to provide the first input signal, and a second terminal connected to the source terminal of the transistor and configured to provide the second input signal, and
the synapse circuit is connected to the pre-synaptic neuron circuit through the first terminal and to the post-synaptic neuron circuit through the second terminal.

7. The synapse circuit of claim 6 , wherein the post-synaptic neuron circuit is configured to generate a spike fired with reference to a resting voltage.

8. The synapse circuit of claim 7 , wherein the post-synaptic neuron circuit comprises an N-metal oxide semiconductor (MOS) and a P-MOS transistor, the N-MOS transistor and the P-MOS transistor being serially connected;
a resting voltage source to supply the resting voltage is connected to a source terminal of the N-MOS transistor; and
a capacitor is connected to a source terminal of the P-MOS transistor.

9. The synapse circuit of claim 1 , wherein different voltages are applied to the memristor and the source terminal of the transistor.

10. The synapse circuit of claim 1 , wherein a channel of the memristor is serially connected to a channel of the transistor.

11. The synapse circuit of claim 1 , wherein the transistor comprises an N-MOS transistor.

12. A neuromorphic system comprising:
a synapse circuit configured to perform spike timing dependent plasticity (STDP) operation, the synapse circuit comprising a first terminal, a second terminal, a memristor having a resistance value, and a transistor connected to the memristor;
a pre-synaptic neuron circuit connected to the memristor through the first terminal of the synapse circuit; and
a post-synaptic neuron circuit connected to the memristor through the second terminal of the synapse circuit,
wherein the resistance value of the memristor is changed based on a time difference between at least two input signals received by the synapse circuit,
wherein terminals of the memristor are respectively coupled to a reference voltage and a drain terminal of the transistor,
wherein the at least two input signals comprise a first input signal applied to a gate terminal of the transistor and a second input signal applied to a source terminal of the transistor, and
wherein the first input signal is provided by a pre-synaptic neuron circuit and the second input signal is provided by a post-synaptic neuron circuit.

13. The neuromorphic system of claim 12 , wherein the first terminal of the synapse circuit is connected to a gate terminal of the transistor to provide a first input signal, and the second terminal of the synapse circuit is connected to a source terminal of the transistor to provide a second input signal.

14. The neuromorphic system of claim 13 , wherein the resistance value of the memristor is changed based on a time difference between the first input signal applied to the gate terminal of the transistor and the second input signal based on a membrane voltage applied to the source terminal of the transistor.

15. The neuromorphic system of claim 14 , wherein a direction of a current flowing on the memristor is determined by a voltage difference caused by the time difference between the first input signal and the second input signal.

16. The neuromorphic system of claim 14 , wherein an amount of a current flowing on the memristor is determined by a voltage difference caused by the time difference between the first input signal and the second input signal.

17. The neuromorphic system of claim 13 , wherein the post-synaptic neuron circuit is configured to generate a spike fired with reference to a resting voltage.

18. The neuromorphic system of claim 17 , wherein the post-synaptic neuron circuit comprises an N-metal oxide semiconductor (MOS) and a P-MOS transistor,
wherein the N-MOS transistor and the P-MOS transistor are serially connected, a resting voltage source to supply the resting voltage is connected to a source terminal of the N-MOS transistor, and a capacitor is connected to a source terminal of the P-MOS transistor.

19. A method of performing spike timing dependent plasticity (STDP) operation between a pre-synaptic neuron circuit and a post-synaptic neuron circuit, the method comprising:
receiving a pre-synaptic input signal from the pre-synaptic neuron circuit, the pre-synaptic input signal comprising a first input signal applied to a gate terminal of a transistor;
receiving a post-synaptic input signal from the post-synaptic neuron circuit, the post-synaptic input signal comprising a second input signal applied to a source terminal of the transistor; and
adjusting a resistance value of a memristor based on a time difference between the pre-synaptic input signal and the post-synaptic input signal,
wherein the post-synaptic input signal is based on a charge stored in a capacitor of the post synaptic neuron circuit.

Assignees

• Samsung Electronics Co Ltd
• Postech Academy-Industry Found

Inventors

• Kim Jun Seok
• Sim Jae Yoon
• Ryu Hyun Surk

Classifications

• G06N3/065

  Analogue means · CPC title

• G06N3/049 Primary

  Temporal neural networks, e.g. delay elements, oscillating neurons or pulsed inputs · CPC title

• G11C13/0007

  comprising metal oxide memory material, e.g. perovskites · CPC title

• G06N3/0635

  Physics · mapped topic

• G11C11/54

  using elements simulating biological cells, e.g. neuron · CPC title