System and method for dynamic power control based on a cache size in volatile memory

Patent metadata

Field	Value
Publication number	US-11334141-B2
Application number	US-202016778104-A
Country	US
Kind code	B2
Filing date	Jan 31, 2020
Priority date	Jan 31, 2020
Publication date	May 17, 2022
Grant date	May 17, 2022

Abstract

A system and method for ensuring information present in volatile memory is moved to persistent memory before power is removed. An information handling system stores a time value corresponding to an amount of time for power to be supplied to the information handling system after a signal is received to power down the information handling system. An embedded controller determines the amount of information present in volatile memory, determines an amount of time needed to move the information to persistent memory, and adjusts the time value as needed to ensure power is supplied to the system until the information has been moved to persistent memory.

First claim

What is claimed is:

1. A power control system for an information handling system (IHS) having a two-level memory comprising a volatile memory and a persistent memory, the power control system comprising:
an embedded controller (EC); and
a memory storing:
a time value corresponding to an amount of time for power to be supplied to the information handling system before powering down the information handling system; and
a set of instructions executable by the EC to:
determine an amount of information present in the volatile memory;
calculate an amount of time needed for the information handling system to move the information from the volatile memory to the persistent memory; and
set the time value equal to the calculated amount of time needed for the processor to move the information from the volatile memory to the persistent memory.

2. The power control system of claim 1 , wherein the EC is configured to:
query the information handling system to determine if information is present in the volatile memory;
if no information is stored in the volatile memory, set the time value equal to a minimum duration of time.

3. The power control system of claim 1 , wherein the EC is configured to:
query the information handling system to determine one or more of a latency and a throughput of the information handling system; and
calculate the amount of time needed for the information handling system to move the information from the volatile memory to the persistent memory based on the amount of information present in the volatile memory and one or more of the latency and the throughput of the information handling system.

4. The power control system of claim 1 , wherein the EC is configured to execute the set of instructions in response to a power button override signal.

5. The power control system of claim 4 , wherein powering down the information handling system comprises one of powering down to a sleep state or shutting down, wherein information in the volatile memory is lost in the sleep state and when the information handling system is shut down.

6. An information handling system comprising:
a processor;
a two-level memory system comprising:
a volatile memory configured for storing information in a cache when the information handling system is in a system working state; and
a persistent memory configured for storing information when the information handling system is in a system sleep state or a system shutdown state;

an embedded controller (EC) communicatively coupled to the processor; and
a memory storing:
a time value corresponding to an amount of time for power to be supplied to the information handling system before powering down the information handling system; and
a set of instructions executable by the EC to:
determine an amount of information present in the volatile memory;
calculate an amount of time needed for the information handling system to move the information from the volatile memory to the persistent memory; and

set the time value equal to the calculated amount of time needed for the processor to move the information from the volatile memory to the persistent memory.

7. The information handling system of claim 6 , wherein the EC is configured to:
query the information handling system to determine if information is present in the volatile memory;
if no information is stored in the volatile memory, set the time value equal to a minimum duration of time.

8. The information handling system of claim 6 , wherein the EC is configured to:
query the information handling system to determine one or more capabilities of the processor, the volatile memory and the persistent memory; and
calculate the amount of time needed for the information handling system to move the information from the volatile memory to the persistent memory based on the amount of information present in the volatile memory and the one or more capabilities of the processor, the volatile memory and the persistent memory.

9. The information handling system of claim 6 , wherein the EC is configured to execute the set of instructions in response to receiving a power button override signal.

10. The information handling system of claim 9 , wherein powering down the information handling system comprises one of powering down to a sleep state or shutting down, wherein information in the volatile memory is lost in the sleep state and when the information handling system is shut down.

11. A method for provisioning power for powering down an information handling system having a two-level memory architecture comprising a volatile memory and a persistent memory, the method comprising:
storing, in a memory associated with an embedded controller (EC), a time value for power to be supplied to the information handling system after a signal to power down the information handling system is received and before power is removed from the information handling system;
determining an amount of information present in the volatile memory;
calculating an amount of time needed for the information handling system to move the information from the volatile memory to the persistent memory; and
setting the time value equal to the amount of time needed for the processor to move the information from the volatile memory to the persistent memory.

12. The method of claim 11 , further comprising:
determining if information is present in the volatile memory; wherein
if no information is present in the volatile memory, setting the time value comprises setting the time value equal to a minimum amount of time.

13. The method of claim 12 , further comprising:
determining one or more of a processor speed, a throughput of the volatile memory, and a throughput of the persistent memory; and
if information is present in the volatile memory, setting the time value based on the amount of information present in the volatile memory and one or more of the processor speed, the throughput of the volatile memory, and the throughput of the persistent memory.

14. The method of claim 11 , wherein setting the time value comprises determining the amount of time needed for power supplied to the information handling system to be stable.

15. The method of claim 11 , wherein determining the amount of information present in the volatile memory is performed in response to receiving a power button override signal.

Assignees

• Dell Products Lp

Inventors

• Zaretsky Lee B
• Kamepalli Srinivas

Classifications

• G06F1/26

  Power supply means, e.g. regulation thereof (for memories G11C) · CPC title

• G06F2212/1036

  Life time enhancement · CPC title

• G06F1/3225 Primary

  of memory devices · CPC title

• G06F1/28 Primary

  Supervision thereof, e.g. detecting power-supply failure by out of limits supervision · CPC title

• G06F12/0804

  with main memory updating (G06F12/0806 takes precedence) · CPC title