Electronic device

Patent metadata

Field	Value
Publication number	US-11329072-B2
Application number	US-202016944171-A
Country	US
Kind code	B2
Filing date	Jul 31, 2020
Priority date	Aug 21, 2019
Publication date	May 10, 2022
Grant date	May 10, 2022

Abstract

An electronic device of an embodiment of the disclosure includes a first substrate, a second substrate, and a driving layer. The first substrate and the second substrate are disposed opposite to each other, and the driving layer is disposed between the first substrate and the second substrate. The driving layer includes a scan line and a data line. The scan line is disposed on the first substrate and includes a first scan line segment. The first scan line segment has an opening and includes a first branch and a second branch. The first branch and the second branch are located on two opposite sides of the opening and are electrically connected in parallel with each other. The data line is disposed on the first substrate and intersects with the scan line. The electronic device of the embodiment of the disclosure may exhibit ideal display effect.

First claim

What is claimed is:

1. An electronic device comprising:
a first substrate;
a second substrate disposed opposite to the first substrate; and
a driving layer disposed between the first substrate and the second substrate, wherein the driving layer comprises:
a scan line disposed on the first substrate, wherein the scan line comprises a first scan line segment, the first scan line segment has an opening and comprises a first branch and a second branch, and the first branch and the second branch are located on two opposite sides of the opening; and
a data line disposed on the first substrate and intersecting with the scan line.

2. The electronic device according to claim 1 , wherein the driving layer further comprises a semiconductor layer, a portion of the semiconductor layer overlapping with the first branch is defined as a first channel region, and a portion of the semiconductor layer overlapping with the second branch is defined as a second channel region.

3. The electronic device according to claim 2 , wherein the semiconductor layer further comprises an intermediate region located between the first channel region and the second channel region.

4. The electronic device according to claim 3 , wherein the first channel region, the intermediate region, and the second channel region are arranged along an arrangement direction, the scan line has an extending direction, and the arrangement direction is different from the extending direction.

5. The electronic device according to claim 3 , wherein doping concentrations of the first channel region and the second channel region are lower than a doping concentration of the intermediate region.

6. The electronic device according to claim 5 , wherein the semiconductor layer is divided into a first segment, a second segment, and a third segment, and the doping concentration of the intermediate region is lower than doping concentrations of the second segment and the third segment.

7. The electronic device according to claim 3 , wherein the intermediate region is located in the opening.

8. The electronic device according to claim 2 , wherein at least one of the first channel region and the second channel region is spaced apart from the data line by a distance.

9. The electronic device according to claim 2 , wherein a portion of the first branch overlapping with the first channel region is defined as a first gate, a portion of the second branch overlapping with the second channel region is defined as a second gate, and the semiconductor layer is defined as an active component having dual gates.

10. The electronic device according to claim 1 , wherein the scan line further comprises a second scan line segment, and the first scan line segment is connected to the second scan line segment.

11. The electronic device according to claim 10 , wherein the first scan line segment has a first scan line width, the second scan line segment has a second scan line width, and the first scan line width is greater than the second scan line width.

12. The electronic device according to claim 11 , wherein a spacing is between the first branch and the second branch, and the first scan line width is a sum of a first branch line width of the first branch, a second branch line width of the second branch, and the spacing.

13. The electronic device according to claim 10 , wherein the first scan line segment and the second scan line segment are electrically connected to each other through a via.

14. The electronic device according to claim 10 , wherein the second scan line segment comprises different segments having different line widths.

15. The electronic device according to claim 10 , wherein in the second scan line segment, one line segment has a line width less than or equal to a sum of the first branch line width and the second branch line width.

16. The electronic device according to claim 1 , wherein the driving layer further comprises an auxiliary scan line, and the auxiliary scan line and the scan line are electrically connected to each other through a via.

17. The electronic device according to claim 1 , wherein the first scan line segment further comprises a connection portion, and the connection portion is connected between the first branch and the second branch.

18. The electronic device according to claim 17 , wherein a number of the connection portion is two, and two connection portions, the first branch, and the second branch collectively enclose the opening.

19. The electronic device according to claim 1 wherein the data line overlaps with the first branch from a top view.

20. The electronic device according to claim 1 , further comprising a common line, the common line intersects with the data line, and the common line and the scan line are in a same layer.

Assignees

• Innolux Corp

Inventors

• Chen Hung-Kun
• Sung Li-Wei
• Hong shuo-ting
• Chen Chung-Le

Classifications

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6733

  Multi-gate TFTs · CPC title

• H10D30/6723

  having light shields · CPC title

• H10D86/441 Primary

  Interconnections, e.g. scanning lines · CPC title

• H10D30/6715

  characterised by the doping profiles, e.g. having lightly-doped source or drain extensions · CPC title