Semiconductor device and method of manufacturing the same

US2016254277A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016254277-A1
Application numberUS-201615153127-A
CountryUS
Kind codeA1
Filing dateMay 12, 2016
Priority dateApr 27, 2001
Publication dateSep 1, 2016
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

There has been a case where peeling occurs if an internal stress of a wiring of a TFT is strong. In particular, the internal stress of a gate electrode largely influences a stress that a semiconductor film receives, and there has been a case where the internal stress becomes a cause of reduction in electric characteristics of a TFT depending on the internal stress. According to the present invention, an impurity element is introduced into a wiring, or both the introduction of an impurity element and heat treatment are performed, whereby the wiring can be controlled to have a desired internal stress. It is effective that the present invention is particularly applied to a gate electrode. Further, it is possible that the introduction of an impurity element and the heat treatment are conducted to only a desired region to conduct control to attain a desired internal stress.

First claim

Opening claim text (preview).

1 . (canceled) 2 . A semiconductor device comprising: a light shielding film over a substrate; a semiconductor film having a crystal structure including a channel forming region overlapping with the light shielding film; a gate electrode over the semiconductor film; a first interlayer insulating film over the gate electrode; a first conductive film electrically connected to the semiconductor film through a first contact hole in the first interlayer insulating film; a second interlayer insulating film over the first conductive film; a second conductive film having light shielding property over the second interlayer insulating film; a third interlayer insulating film over the second conductive film; and a pixel electrode electrically connected to the first conductive film through a second contact hole in the third interlayer insulating film, wherein the first contact hole does not overlap with the second contact hole. 3 . The semiconductor device according to claim 2 , wherein the light shielding film comprises an element included in the gate electrode. 4 . The semiconductor device according to claim 2 , wherein the light shielding film comprises at least one of Ta, W, Cr, and Mo. 5 . The semiconductor device according to claim 2 , wherein the first conductive film comprises Al and Ti. 6 . The semiconductor device according to claim 2 , wherein the second conductive film comprises at least one of Al, Ti, W, and Cr. 7 . The semiconductor device according to claim 2 , wherein the semiconductor device is a liquid crystal display device. 8 . A semiconductor device comprising: a light shielding film over a substrate; a semiconductor film having a crystal structure including a channel forming region overlapping with the light shielding film; a gate electrode over the semiconductor film; a first interlayer insulating film over the gate electrode; a first conductive film electrically connected to the semiconductor film through a first contact hole in the first interlayer insulating film; a second interlayer insulating film over the first conductive film; a second conductive film having light shielding property arranged in mesh over the second interlayer insulating film; a third interlayer insulating film over the second conductive film; and a pixel electrode electrically connected to the first conductive film through a second contact hole in the third interlayer insulating film, wherein the first contact hole does not overlap with the second contact hole. 9 . The semiconductor device according to claim 8 , wherein the light shielding film comprises an element included in the gate electrode. 10 . The semiconductor device according to claim 8 , wherein the light shielding film comprises at least one of Ta, W, Cr, and Mo. 11 . The semiconductor device according to claim 8 , wherein the first conductive film comprises Al and Ti. 12 . The semiconductor device according to claim 8 , wherein the second conductive film comprises at least one of Al, Ti, W, and Cr. 13 . The semiconductor device according to claim 8 , wherein the semiconductor device is a liquid crystal display device.

Assignees

Inventors

Classifications

  • Thermal treatments, e.g. annealing or sintering · CPC title

  • wherein the TFTs are in active matrices · CPC title

  • H10D86/441Primary

    Interconnections, e.g. scanning lines · CPC title

  • Multi-gate TFTs · CPC title

  • having a particular composition, shape or crystalline structure of the active layer · CPC title

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What does patent US2016254277A1 cover?
There has been a case where peeling occurs if an internal stress of a wiring of a TFT is strong. In particular, the internal stress of a gate electrode largely influences a stress that a semiconductor film receives, and there has been a case where the internal stress becomes a cause of reduction in electric characteristics of a TFT depending on the internal stress. According to the present inve…
Who is the assignee on this patent?
Semiconductor Energy Lab
What technology area does this patent fall under?
Primary CPC classification H10D86/441. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Sep 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).