Interconnection of copper surfaces using copper sintering material

Patent metadata

Field	Value
Publication number	US-11329023-B2
Application number	US-202017001110-A
Country	US
Kind code	B2
Filing date	Aug 24, 2020
Priority date	Apr 10, 2020
Publication date	May 10, 2022
Grant date	May 10, 2022

Abstract

A method for interconnecting a first conductor and a second conductor includes forming a layer of substantially pure copper on the first conductor, applying a copper sintering material to the first conductor, the second conductor, or both, and interconnecting the first conductor and the second conductor by sintering the copper sintering material so as to form a copper-copper interface that includes the layer of substantially pure copper, the second conductor, and the copper sintering material.

First claim

The invention claimed is:

1. A method for interconnecting a first conductor and a second conductor, comprising:
forming a layer of substantially pure copper on the first conductor;
applying a copper sintering material to the first conductor, the second conductor, or both; and
interconnecting the first conductor and the second conductor by sintering the copper sintering material so as to form a copper-copper interface that includes the layer of substantially pure copper, the second conductor, and the copper sintering material.

2. The method of claim 1 , wherein the method does not include plating the first conductor or the second conductor with gold or nickel.

3. The method of claim 1 , wherein the first conductor comprises an alloy of copper and another element, and wherein forming the layer of substantially pure copper on the first conductor comprises plating the first conductor with the substantially pure copper layer prior to applying the copper sintering material.

4. The method of claim 3 , wherein the other element is selected from the group consisting of iron, nickel, magnesium, manganese, phosphorus, lead, beryllium, zinc, tin, and silicon.

5. The method of claim 1 , wherein the second conductor comprises a solder pad of a printed circuit board, and wherein the first conductor comprises a lead of an electrical component that is electrically and physically coupled to the printed circuit board by sintering the copper sintering material.

6. The method of claim 1 , wherein the copper-copper interface is substantially free of intermetallic compounds.

7. The method of claim 1 , further comprising forming a protective layer on the first conductor, the protective layer being configured to prevent the first conductor, the layer of substantially pure copper, or both from oxidation.

8. The method of claim 7 , wherein the protective layer comprises an organic solderability preservative, a nitrogen-containing molecule, or both.

9. The method of claim 1 , wherein the first conductor comprises an iron-nickel alloy applied to a ceramic substrate.

10. An electrical device, comprising:
a component comprising a first conductor and a substantially pure copper layer plated on the first conductor; and
a circuit board comprising a second conductor comprising copper; and
a sintered joint comprising a copper sintering material, the sintered joint interconnecting the first and second conductors by forming a copper-copper interface between the second conductor and the substantially pure copper layer.

11. The electrical device of claim 10 , further comprising a first protective layer over the copper layer, to prevent the copper layer from oxidizing, and a second protective layer over the second conductor, to prevent the second conductor from oxidizing.

12. The electrical device of claim 11 , wherein neither the first protective layer nor the second protective layer comprises gold or nickel.

13. The electrical device of claim 11 , wherein the first protective layer and the second protective layer each include a material having a nitrogen-containing molecule, an organic solderability preservative, or both.

14. The electrical device of claim 10 , wherein the sintered joint does not include gold intermetallic compounds.

15. The electrical device of claim 10 , wherein the first conductor comprises an alloy of the copper and another element.

16. The electrical device of claim 15 , wherein the other element is selected from the group consisting of: iron, nickel, magnesium, manganese, phosphorus, lead, beryllium, zinc, tin, and silicon.

17. The electrical device of claim 10 , wherein the first conductor comprises an alloy of iron and nickel formed on a ceramic substrate.

18. The electrical device of claim 10 , wherein the electrical device is contained within a downhole tool configured to be deployed into a wellbore.

19. The electrical device of claim 10 , wherein the copper sintering material comprises copper nanoparticles.

20. A method for interconnecting two conductors, comprising:
forming one or more substantially pure copper layers on a first conductor, the first conductor comprising an alloy of copper and another element or an iron-lead alloy over which the one or more substantially pure copper layers are formed;
forming a first protective layer on the first conductor, over the one or more copper layers, and forming a second protective layer on a second conductor, the second conductor comprising a substantially pure copper, wherein the first and second protective layers prevent the first conductor, the second conductor, the one or more copper layers, or a combination thereof from oxidation;
applying a copper sintering paste to the first conductor, the second conductor, or both after forming the first and second protective layers; and
interconnecting the first conductor and the second conductor by sintering the copper sintering paste so as to form a copper-copper interface comprising the one or more substantially pure copper layers on the first conductor, the copper sintering paste, and the second conductor, wherein the interface is substantially free from intermetallic compounds.

Assignees

• Schlumberger Technology Corp

Inventors

• Kostinovsky Mark Alex
• Dunford Steven O
• Mazari Lweness

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/07331

  Connecting techniques · CPC title

• H10W72/352

  comprising metals or metalloids, e.g. solders · CPC title

• H10W72/351

  Materials of die-attach connectors · CPC title

• H10W72/325

  Die-attach connectors having a filler embedded in a matrix · CPC title