CPU hot-swapping

Patent metadata

Field	Value
Publication number	US-11327918-B2
Application number	US-201817041519-A
Country	US
Kind code	B2
Filing date	Jun 29, 2018
Priority date	Jun 29, 2018
Publication date	May 10, 2022
Grant date	May 10, 2022

Abstract

There is disclosed in one example a multi-core computing system configured to provide a hot-swappable CPU0, including: a first CPU in a first CPU socket and a second CPU in a second CPU socket; a switch including a first media interface to the first CPU socket and a second media interface to the second CPU socket; and one or more mediums including non-transitory instructions to detect a hot swap event of the first CPU, designate the second CPU as CPU0, determine that a new CPU has replaced the first CPU, operate the switch to communicatively couple the new CPU to a backup initialization code store via the first media interface, initialize the new CPU, and designate the new CPU as CPUN, wherein N≠0.

First claim

What is claimed is:

1. A multi-core computing system configured to provide a hot-swappable CPUO, comprising:
a first CPU in a first CPU socket and a second CPU in a second CPU socket;
a switch comprising a first media interface to the first CPU socket and a second media interface to the second CPU socket; and
one or more non-transitory mediums including instructions, that when executed, cause the multi-core computing system to detect a hot swap event of the first CPU, designate the second CPU as CPU0, determine that a new CPU has replaced the first CPU, operate the switch to communicatively couple the new CPU to a backup initialization code store via the first media interface, initialize the new CPU, and designate the new CPU as CPUN, wherein N≠0.

2. The multi-core computing system of claim 1 , wherein the first media interface is a first direct media interface (DMI) and the second media interface is a second DMI, and wherein the switch is a DMI switch.

3. The multi-core computing system of claim 2 , wherein the switch comprises a switching DMI fabric.

4. The multi-core computing system of claim 1 , further comprising a message channel routing table to control media interface routing within the switch.

5. The multi-core computing system of claim 4 , further comprising a baseboard management controller (BMC) to program the message channel routing table.

6. The multi-core computing system of claim 5 , wherein programming the message channel routing table comprises placing all or part of the multi-core computing system into a quiescent state.

7. The multi-core computing system of claim 1 , further comprising a first chipset, wherein the instructions are further to cause the multi-core computing system to operate the switch to communicatively couple the second CPU to the first chipset.

8. The multi-core computing system of claim 7 , further comprising a second chipset, wherein the instructions are further to cause the multi-core computing system to operate the switch to communicatively couple the new CPU to the second chipset and wherein the first and second chipsets are platform controller hub (PCH) circuits.

9. The multi-core computing system of claim 8 , wherein the PCH circuits comprise limited PCH functionality.

10. The multi-core computing system of claim 8 , wherein the first and second PCH circuits comprise at least one configurable logic circuit.

11. The multi-core computing system of claim 1 , wherein the instructions are further to cause the multi-core computing system to provide dynamic partitioning.

12. The multi-core computing system of claim 1 , wherein the backup initialization code comprises operating system boot code.

13. The multi-core computing system of claim 1 , wherein initializing the new CPU comprises initializing without SMI slicing.

14. A computing apparatus, comprising:
a hardware platform comprising a first central processor unit (CPU) in a CPUO configuration and a second CPU in a CPUN configuration wherein N≠0;
a first boot store and a second boot store, the first and second boot stores comprising substantially identical instructions to initialize a CPU;
a switch comprising a first media interface to the first CPU and a second media interface to the second CPU, and switching logic to communicatively couple the switch to the first and second boot stores; and
instructions encoded on a tangible and non-transitory medium to instruct the hardware platform to:
determine that the first CPU is to be hot swapped;
designate the second CPU as CPU0;
operate the switch to communicatively couple the first CPU to the second boot store via the second media interface, and to communicatively couple the second CPU to the first boot store via the first media interface;
determine that a new CPU has replaced the first CPU; and
initialize the new CPU comprising retrieving instructions to initialize the new CPU from the first boot store via the first media interface.

15. The computing apparatus of claim 14 , further comprising a baseboard management controller (BMC) to program a message channel routing table.

16. The computing apparatus of claim 15 , wherein programming the message channel routing table comprises placing all or part of the hardware platform into a quiescent state.

17. The computing apparatus of claim 16 , further comprising a first chipset, wherein the instructions are further to instruct the hardware platform to operate the switch to communicatively couple the second CPU to the first chipset.

18. The computing apparatus of claim 17 , further comprising a second chipset, wherein the first and second chipsets are platform controller hub (PCH) circuits.

19. A method of hot-swapping a CPUO, comprising:
detecting a hot swap event for a first CPU in a first CPU socket, wherein the first CPU is designated CPU0;
designating a second CPU in a second CPU socket as CPUN, where N≠0;
operating a media interface switch to communicatively couple the first CPU to a first boot code store via a media interface;
determining that a new CPU populates the first CPU socket; and
booting the new CPU with information from the first boot code store.

20. The method of claim 19 , wherein the media interface is a direct media interface (DMI), and wherein the media interface switch is a DMI switch comprising a switching DMI fabric.

21. At least one non-transitory computer-readable storage medium, comprising a plurality of instructions, that when executed by a multi-core computing system, cause the multi-core computing system to:
detect a hot swap event for a first CPU in a first CPU socket, wherein the first CPU is designated CPU0;
designate a second CPU in a second CPU socket as CPUN, where N≠0;
operate a media interface switch to communicatively couple the first CPU to a first boot code store via a media interface;
determine that a new CPU populates the first CPU socket; and
boot the new CPU with information from the first boot code store.

22. The at least one non-transitory computer-readable storage medium of claim 21 , wherein the media interface is a direct media interface (DMI), and wherein the media interface switch is a DMI switch comprising a switching DMI fabric.

Assignees

• Intel Corp

Inventors

• Chen Zhi Yong
• Jayakumar Sarathy
• Zeng Yi
• Mao Wenjuan
• Agrawal Anil

Classifications

• G06F11/2041

  with more than one idle spare processing component · CPC title

• G06F11/2038 Primary

  with a single idle spare processing component · CPC title

• G06F9/4405

  Initialisation of multiprocessor systems · CPC title

• G06F13/4022

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

• G06F11/2043

  where the redundant components share a common memory address space · CPC title