Devices and methods for data storage

Patent metadata

Field	Value
Publication number	US-11327835-B2
Application number	US-202016944697-A
Country	US
Kind code	B2
Filing date	Jul 31, 2020
Priority date	Aug 1, 2019
Publication date	May 10, 2022
Grant date	May 10, 2022

Abstract

In an embodiment, a storage device includes a multiplicity of data value memory cells and a multiplicity of check value memory cells, where at least one of the multiplicity of data value memory cells is assigned to two of the check value memory cells, and where at least one of the multiplicity of check value memory cells is assigned to two of the data value memory cells, and a correction circuit which is configured to output a corrected data value when reading out a selected data value memory cell of the at least one of the multiplicity of data value memory cells, based on a content of the selected data value memory cell and based on contents of the two check value memory cells assigned to the selected data value memory cell.

First claim

What is claimed is:

1. A storage device, comprising:
a multiplicity of data value memory cells,
a multiplicity of check value memory cells,
wherein exactly two of the check value memory cells are assigned to at least one of the multiplicity of data value memory cells, and
wherein two of the data value memory cells are assigned to at least one of the multiplicity of check value memory cells, and
a correction circuit which is configured to output a corrected data value when reading out a selected data value memory cell of the at least one of the multiplicity of data value memory cells, based on a content of the selected data value memory cell and on contents of the exactly two check value memory cells assigned to the selected data value memory cell.

2. The storage device as claimed in claim 1 , wherein the at least one of the multiplicity of check value memory cells is configured to store a check value based on data values to be stored in the two data value memory cells assigned to it.

3. The storage device as claimed in claim 2 , wherein the storage device is configured to form the check value of the at least one of the multiplicity of check value memory cells based on an XOR operation or XNOR operation performed on the data values to be stored in the two data value memory cells assigned to the at least one of the multiplicity of check value memory cells.

4. The storage device as claimed in claim 1 , wherein:
the exactly two check value memory cells which are assigned to the at least one of the multiplicity of data value memory cells comprise a first check value memory cell and a second check value memory cell,
a first further of the multiplicity of data value memory cells is further assigned to the first check value memory cell,
a second further of the multiplicity of data value memory cells is further assigned to the second check value memory cell, and
the corrected data value is formed on the basis of the content of the selected data value memory cell, a content of the first check value memory cell, a content of the second check value memory cell, a content of the first further of the multiplicity of data value memory cells and a content of the second further of the multiplicity of data value memory cells.

5. The storage device as claimed in claim 4 , wherein the correction circuit is further configured:
to form a first correction value based on a first XOR operation or first XNOR operation performed on the content of the selected data value memory cell, the content of the first check value memory cell and the content of the first further of the multiplicity of data value memory cells, and
to form a second correction value based on a second XOR operation or second XNOR operation performed on the content of the selected data value memory cell, the content of the second check value memory cell and the content of the second further of the multiplicity of data value memory cells.

6. The storage device as claimed in claim 5 , wherein the correction circuit is further configured:
to form a logical value based on a first logical operation performed on the first correction value and on the second correction value, and
to form the corrected data value based on a second logical operation performed on the content of the selected data value memory cell and on the logical value.

7. The storage device as claimed in claim 6 , wherein:
the first logical operation comprises an AND operation and/or a NAND operation, and
the second logical operation comprises an XOR operation and/or an XNOR operation.

8. The storage device as claimed in claim 5 , further comprising an error detection circuit.

9. The storage device as claimed in claim 1 , wherein each of the at least one of the multiplicity of check value memory cells is spatially arranged between the two data value memory cells assigned to it from the multiplicity of data value memory cells.

10. The storage device as claimed in claim 1 , wherein:
two check value memory cells of the at least one of the multiplicity of check value memory cells are assigned in each case to the same two data value memory cells.

11. The storage device as claimed in claim 10 , wherein:
the respective two check value memory cells of the at least one of the multiplicity of check value memory cells which are assigned to the same two data value memory cells are spatially arranged between these two data value memory cells, and
the respective spatially more distantly arranged of the respective two check value memory cells is assigned to each data value memory cell of the same two data value memory cells.

12. The storage device as claimed in claim 1 , wherein two of the data value memory cells are assigned to each of the multiplicity of check value memory cells.

13. The storage device as claimed in claim 1 ,
wherein at least one further check value memory cell of the multiplicity of check value memory cells is assigned to one of the data value memory cells and is configured to store as a check value a data value which is to be stored in the data value memory cell assigned to it.

14. The storage device as claimed in claim 1 , further comprising a write circuit which is configured to store respective data values as the respective contents in the multiplicity of data value memory cells, and
to store a check value as an XOR operation or XNOR operation performed on the data values to be stored in the data value memory cells assigned to the respective check value memory cell as content in each of the check value memory cells of the at least one of the multiplicity of check value memory cells.

15. The storage device as claimed in claim 1 , wherein the storage device is configured:
to define at least one first parity value based on the multiplicity of respective data values to be stored in the multiplicity of data value memory cells, and
to define at least one second parity value based on a multiplicity of corrected data values.

16. A method for reading memory cells in a storage device having
a multiplicity of data value memory cells,
a multiplicity of check value memory cells,
wherein exactly two of the check value memory cells are assigned to at least one of the multiplicity of data value memory cells, wherein the method comprises:
receiving a content of a selected data value memory cell of the multiplicity of data value memory cells,
receiving contents from the exactly two check value memory cells of the multiplicity of check value memory cells, wherein the exactly two check value memory cells are assigned to the selected data value memory cell,
defining a corrected data value based on:
the content of the selected data value memory cell, and
the contents of the exactly two check value memory cells assigned to the selected data value memory cell.

17. The method as claimed in claim 16 , wherein
the exactly two check value memory cells which are assigned to the at least one of the multiplicity of data value memory cells comprise a first check value memory cell and a second check value memory cell,
a first further of the multiplicity of data memory cells is further assigned to the first check value memory cell,
a second further of the multiplicity of data memory cells is further assigned to the second check value memory cell, and
the method further comprises:
defining the corrected data value based on the content of the selected data value memory cell, a content of the first check value memory cell, a content of the second check value memory cell, a content of the first further of the multiplicity of data value memory cells and a c

Assignees

• Infineon Technologies Ag

Inventors

• Georgakos Georg
• Goessel Michael

Classifications

• G11C29/52 Primary

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G06F11/1068 Primary

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title

• G11C29/42

  using error correcting codes [ECC] or parity check · CPC title