Instruction dispatch routing

Patent metadata

Field	Value
Publication number	US-11327766-B2
Application number	US-202016945404-A
Country	US
Kind code	B2
Filing date	Jul 31, 2020
Priority date	Jul 31, 2020
Publication date	May 10, 2022
Grant date	May 10, 2022

Abstract

A method of instruction dispatch routing comprises receiving an instruction for dispatch to one of a plurality of issue queues; determining a priority status of the instruction; selecting a rotation order based on the priority status, wherein a first rotation order is associated with priority instructions and a second rotation order, different from the first rotation order, is associated with non-priority instructions; selecting an issue queue of the plurality of issue queues based on the selected rotation order; and dispatching the instruction to the selected issue queue.

First claim

What is claimed is:

1. A method comprising:
receiving an instruction for dispatch to one of a plurality of issue queues;
determining a resource intensity of the instruction;
selecting a rotation order based on the resource intensity, wherein a first rotation order is associated with instructions designated as resource intensive and a second rotation order, different from the first rotation order, is associated with instructions designated as non-resource intensive;
selecting an issue queue of the plurality of issue queues based on the selected rotation order; and
dispatching the instruction to the selected issue queue.

2. The method of claim 1 , wherein the instruction type designated as resource intensive is determined dynamically from cycle to cycle.

3. The method of claim 1 , wherein each issue queue has 2 slots; and
wherein selecting the issue queue includes selecting the issue queue and slot based on the selected rotation order.

4. The method of claim 1 , wherein dispatching the instruction to the selected issue queue further comprises:
determining that the selected issue queue is busy; and
waiting for the selected issue queue to become available in response to determining that the selected issue queue is busy.

5. The method of claim 1 , wherein dispatching the instruction to the selected issue queue further comprises:
determining that the selected issue queue is busy;
selecting a next issue queue based on the selected rotation order in response to determining that the selected issue queue is busy; and
dispatching the instruction to the next issue queue.

6. A method comprising:
receiving a plurality of instructions in a cycle, the plurality of instructions including one or more instructions designated as resource intensive and one or more instructions designated as non-resource intensive;
dispatching each of the one or more instructions designated as resource intensive to a respective one of a plurality of issue queues according to a first rotation order; and
dispatching each of the one or more instructions designated as non-resource intensive to a respective one of the plurality of issue queues according to a second rotation order opposite to the first rotation order.

7. The method of claim 6 , further comprising tracking a position in the first rotation order and a position in the second rotation order for use in a subsequent cycle.

8. The method of claim 6 , wherein the plurality of issue queues are divided into a first group and a second group operating independently of the first group; and
wherein each of the first group and the second group is associated with both a respective first rotation order for resource intensive instructions and a respective second rotation order for non-resource intensive instructions.

9. The method of claim 6 , wherein at least two of the plurality of instructions are paired instructions;
wherein the method further comprises pairing each of the non-paired instructions with another non-paired instruction; and
wherein dispatching each of the one or more instructions designated as resource intensive comprises dispatching each of the one or more instructions designated as resource intensive together with another of the plurality of instructions according to the first rotation order; and
wherein dispatching each of the one or more instructions designated as non-resource intensive comprises dispatching each of the one or more instructions designated as non-resource intensive paired with another non-resource intensive instruction according to the second rotation order.

10. A processor comprising:
an instruction fetch unit;
a dispatch unit communicatively coupled to the instruction fetch unit; and
a plurality of issue queues communicatively coupled to the dispatch unit;
wherein the dispatch unit is configured to:
receive a plurality of instructions from the instruction fetch unit;
determine a respective resource intensity for each of the plurality of instructions;
select a rotation order for each of the plurality of instructions based on the respective resource intensity, wherein a first rotation order is associated with instructions designated as resource intensive and a second rotation order, different from the first rotation order, is associated with instructions designated as non-resource intensive;
select a respective issue queue of the plurality of issue queues for each of the plurality of instructions based on the respective selected rotation order; and
dispatch each of the plurality of instruction to the respective selected issue queue.

11. The processor of claim 10 , wherein the instruction fetch unit is configured to determine an instruction type designated as resource intensive dynamically from cycle to cycle.

12. The processor of claim 10 , wherein each issue queue of the plurality of issue queues has 2 slots; and
wherein select the respective issue queue of the plurality of issue queues for each of the plurality of instructions includes selecting the respective issue queue and slot based on the respective selected rotation order.

13. The processor of claim 10 , wherein the dispatch unit is further configured to determine that the respective selected issue queue for a given one of the plurality of instructions is busy and to wait to dispatch the given one of the plurality of instructions until the respective selected issue queue becomes available.

14. The processor of claim 10 , wherein the dispatch unit is further configured to determine that the respective selected issue queue for a given one of the plurality of instructions is busy, to select a next issue queue based on the respective selected rotation order in response to determining that the respective selected issue queue is busy, and to dispatch the given one of the plurality of instructions to the next issue queue.

15. A computer system comprising:
a memory configured to store program code; and
a processor communicatively coupled to the memory and configured to execute the program code, wherein the processor comprises:
an instruction fetch unit;
a dispatch unit communicatively coupled to the instruction fetch unit; and
a plurality of issue queues communicatively coupled to the dispatch unit;
wherein the dispatch unit is configured to:
receive a plurality of instructions in a cycle, the plurality of instructions including one or more instructions designated as resource intensive and one or more instructions designated as non-resource intensive;
dispatch each of the one or more instructions designated as resource intensive to a respective one of the plurality of issue queues according to a first rotation order; and
dispatch each of the one or more instructions designated as non-resource intensive to a respective one of the plurality of issue queues according to a second rotation order opposite to the first rotation order.

16. The computer system of claim 15 , wherein the dispatch unit is further configured to track a position in the first rotation order and a position in the second rotation order for use in a subsequent cycle.

17. The computer system of claim 15 , wherein the plurality of issue queues are divided into a first group and a second group operating independently of the first group; and
wherein each of the first group and the second group is associated with both a respective first rotation order for resource intensive instructions and a respective second rotation order for non-resource intensive instructions.

18. The computer system of claim 15 , wherein at least two of the plurality of instruc

Assignees

• IBM

Inventors

• Schwarz Eric Mark
• Thompto Brian W
• Feiste Kurt A
• Genden Michael Joseph
• Nguyen Dung Q
• Eisen Susan E

Classifications

• G06F9/30036

  Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title

• G06F9/3836 Primary

  Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution · CPC title

• G06F9/3802

  Instruction prefetching · CPC title

• G06F9/3855 Primary

  Physics · mapped topic

• G06F9/3856 Primary

  Reordering of instructions, e.g. using queues or age tags · CPC title