Semiconductor device with region of varying thickness

Patent metadata

Field	Value
Publication number	US-11322612-B2
Application number	US-202016816764-A
Country	US
Kind code	B2
Filing date	Mar 12, 2020
Priority date	Sep 17, 2019
Publication date	May 3, 2022
Grant date	May 3, 2022

Abstract

According to one embodiment, a semiconductor device includes a first electrode, a first semiconductor region of a first conductivity type, a second electrode, a gate electrode, second semiconductor regions of a second conductivity type, third semiconductor regions of the first conductivity type, and a third electrode. The second electrode is provided in a plurality in second and third directions. Each second electrode opposes a portion of the first semiconductor region in the second and third directions with an insulating layer interposed. The gate electrode is provided around each second electrode. The first semiconductor region includes first regions provided respectively around the second electrodes and the second region provided around the first regions in the second and third directions. Impurity concentration of the first conductivity type in each of the first regions is higher than impurity concentration of the first conductivity type in the second region.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first electrode;
a first semiconductor region provided on the first electrode and electrically connected to the first electrode, the first semiconductor region being of a first conductivity type;
a second electrode opposing a portion of the first semiconductor region in a second direction and a third direction with an insulating layer interposed, a plurality of the second electrodes being provided in the second direction and the third direction, the second direction being perpendicular to a first direction from the first electrode toward the first semiconductor region, the third direction being perpendicular to the first direction and crossing the second direction;
a gate electrode provided around each of the second electrodes;
a plurality of second semiconductor regions opposing the gate electrode with a gate insulating layer interposed, being provided respectively between the gate electrode and the second electrodes, and being of a second conductivity type;
a plurality of third semiconductor regions provided respectively on the second semiconductor regions, the third semiconductor regions being of the first conductivity type; and
a third electrode provided on the second semiconductor regions and the third semiconductor regions and electrically connected to the second semiconductor regions, the third semiconductor regions, and the second electrodes, the first semiconductor region including a plurality of first regions provided respectively around the second electrodes in the second direction and the third direction, and
a second region provided around the first regions, impurity concentrations of the first conductivity type in the first regions being higher than an impurity concentration of the first conductivity type in the second region.

2. The device according to claim 1 , wherein the first regions also is provided respectively between the first electrode and the second electrodes in the first direction.

3. The device according to claim 1 , wherein thicknesses of the first regions in the second direction are greater than thicknesses of the first regions in a fourth direction, the fourth direction being perpendicular to the first direction and crossing the second direction and the third direction.

4. The device according to claim 1 , wherein the first semiconductor region further includes a third region provided between the first electrode and the first regions, between the first electrode and the second region, and between the first electrode and the second electrodes, and an impurity concentration of the first conductivity type in the third region is higher than the impurity concentration of the first conductivity type in the second region.

5. A semiconductor device, comprising:
a first electrode;
a first semiconductor region provided on the first electrode and electrically connected to the first electrode, the first semiconductor region being of a first conductivity type;
an insulating portion provided on a portion of the first semiconductor region, a plurality of the insulating portions being provided in a second direction and a third direction, the second direction being perpendicular to a first direction from the first electrode toward the first semiconductor region, the third direction being perpendicular to the first direction and crossing the second direction;
a second semiconductor region provided on an other portion of the first semiconductor region, the second semiconductor region being of a second conductivity type;
a plurality of second electrodes provided respectively inside the insulating portions, the second electrodes including portions opposing the first semiconductor region;
a plurality of gate electrodes opposing the second semiconductor region and being provided respectively inside the insulating portions;
a plurality of third semiconductor regions provided selectively on the second semiconductor region and positioned respectively around the gate electrodes, the third semiconductor regions being of the first conductivity type; and
a third electrode provided on the second semiconductor region and the third semiconductor regions and electrically connected to the second semiconductor region, the third semiconductor regions, and the second electrodes,
the first semiconductor region including a plurality of first regions provided respectively around the insulating portions, and a second region provided around the first regions, portions of the first regions being positioned respectively between the first electrode and the second electrodes in the first direction, impurity concentrations of the first conductivity type in the first regions being higher than an impurity concentration of the first conductivity type in the second region,
wherein the plurality of gate electrodes are respectively positioned between the second semiconductor region and portions of the plurality of second electrodes in the second direction and the third direction.

6. The device according to claim 5 , wherein the first semiconductor region further includes a third region provided between the first electrode and the first regions, between the first electrode and the second region, and between the first electrode and the second electrodes, and an impurity concentration of the first conductivity type in the third region is higher than the impurity concentration of the first conductivity type in the second region.

7. The device according to claim 5 , further comprising a plurality of connectors respectively provided between the plurality of second electrodes and the third electrode in the first direction, the plurality of connectors being electrically connected with the plurality of second electrodes and the third electrode.

8. A semiconductor device, comprising:
a first electrode;
a first semiconductor region provided on the first electrode and electrically connected to the first electrode, the first semiconductor region being of a first conductivity type;
an insulating portion provided on a portion of the first semiconductor region, a plurality of the insulating portions being provided in a second direction and a third direction, the second direction being perpendicular to a first direction from the first electrode toward the first semiconductor region, the third direction being perpendicular to the first direction and crossing the second direction;
a second semiconductor region provided on an other portion of the first semiconductor region, the second semiconductor region being of a second conductivity type;
a plurality of second electrodes provided respectively inside the insulating portions, the second electrodes including portions opposing the first semiconductor region;
a plurality of gate electrodes opposing the second semiconductor region and being provided respectively inside the insulating portions;
a plurality of third semiconductor regions provided selectively on the second semiconductor region and positioned respectively around the gate electrodes, the third semiconductor regions being of the first conductivity type; and
a third electrode provided on the second semiconductor region and the third semiconductor regions and electrically connected to the second semiconductor region, the third semiconductor regions, and the second electrodes, the first semiconductor region including a plurality of first regions provided respectively around the insulating portions, and
a second region provided around the first regions, thicknesses of the first regions in the second direction being greater than thicknesses of the first regions in a fourth direction, the fourth direction being perpendicular to the first direction and crossing the second direction and the third direction,
wherein the

Assignees

• Toshiba Kk
• Toshiba Electronic Devices & Storage Corp

Inventors

• Ichinoseki Kentaro
• Nishiwaki Tatsuya
• Sato Shingo

Classifications

• H10P32/1406

  by ion implantation · CPC title

• H10P32/171

  being group IV material · CPC title

• H10D64/519

  characterised by their top-view geometrical layouts · CPC title

• H10D64/516

  the thicknesses being non-uniform · CPC title

• H10D64/117

  Recessed field plates, e.g. trench field plates or buried field plates · CPC title