Semiconductor device having a high breakdown voltage

Patent metadata

Field	Value
Publication number	US-9048215-B2
Application number	US-201314014260-A
Country	US
Kind code	B2
Filing date	Aug 29, 2013
Priority date	Apr 26, 2013
Publication date	Jun 2, 2015
Grant date	Jun 2, 2015

Abstract

A semiconductor device includes a first layer of a first-type, a second layer of a second-type formed on the first layer, a third layer of the first type formed on the second layer, a first electrode connected to the second and third layers, a second electrode connected to the first layer, a third electrode embedded in a trench formed through the third and second layers and into the first layer, a fourth electrode embedded in the trench below the third electrode, and an insulating layer formed in the trench around the fourth electrode. The first layer includes a first region that is in contact with the insulating layer and at which a concentration of the first-type dopant is lower than the concentration at a second region that is formed around the first region.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first semiconductor layer of a first conductivity type;
a second semiconductor layer of a second conductivity type provided on the first semiconductor layer;
a third semiconductor layer of the first conductivity type provided on the second semiconductor layer;
a first electrode electrically connected to the second semiconductor layer and the third semiconductor layer;
a second electrode electrically connected to the first semiconductor layer;
a third electrode embedded in a trench provided through the third semiconductor layer and the second semiconductor layer and into the first semiconductor layer;
a fourth electrode embedded in the trench below the third electrode; and
an insulating layer provided in the trench around the fourth electrode,
wherein the first semiconductor layer includes a first region that is in contact with the insulating layer and at which a concentration of a first conductivity type dopant is lower than the concentration of the first conductivity type dopant at a second region of the first semiconductor layer that is provided around the first region and wherein a concentration of a second conductivity type dopant is uniform across the second semiconductor layer.

2. The semiconductor device according to claim 1 , wherein
the first region of the first semiconductor layer is in contact with the insulating layer at a bottom of the trench.

3. The semiconductor device according to claim 2 , wherein
the first region of the first semiconductor layer covers the insulating layer at a bottom edge of the trench.

4. The semiconductor device according to claim 1 , wherein
the insulating layer is surrounded by the first region of the first semiconductor layer.

5. The semiconductor device according to claim 1 , wherein
the fourth electrode is electrically connected to the first electrode and insulated from the third electrode.

6. The semiconductor device according to claim 1 , wherein
the fourth electrode is electrically connected to the third electrode.

7. The semiconductor device according to claim 1 , wherein
the first semiconductor layer includes a third region between the second region and the second electrode, a concentration of the first conductivity type dopant at the third region is higher than the concentration of the first conductivity type dopant at the second region.

8. A semiconductor device comprising:
a first semiconductor layer of a first conductivity type;
a second semiconductor layer of a second conductivity type provided on the first semiconductor layer;
a plurality of third semiconductor layers of the first conductivity type provided on the second semiconductor layer;
a first electrode electrically connected to the second semiconductor layer and the third semiconductor layers;
a second electrode electrically connected to the first semiconductor layer;
a plurality of third electrodes, each of which is embedded in a trench provided through one of the third semiconductor layers and the second semiconductor layer and into the first semiconductor layer;
a plurality of fourth electrodes, each of which is embedded in the trench below the third electrode; and
a plurality of insulating layers, each of which is provided around one of the fourth electrodes,
wherein the first semiconductor layer includes a plurality of first regions, each of which is in contact with one of the insulating layers, and a concentration of a first conductivity type dopant at the first regions is lower than the concentration of the first conductivity type dopant at a second region of the first semiconductor layer that is provided around the first regions and wherein a concentration of a second conductivity type dopant is uniform across the second semiconductor layer.

9. The semiconductor device according to claim 8 , wherein
each of the first regions of the first semiconductor layer is in contact with each of the insulating layers at a bottom of one of the trenches.

10. The semiconductor device according to claim 9 , wherein
each of the first regions of the first semiconductor layer covers one of the insulating layers a bottom edge of one of the trenches.

11. The semiconductor device according to claim 8 , wherein
each of the insulating layers is surrounded by one of the first regions of the first semiconductor layer.

12. The semiconductor device according to claim 8 , wherein
each of the fourth electrodes is electrically connected to the first electrode and insulated from each of the third electrodes.

13. The semiconductor device according to claim 8 , wherein
each of the fourth electrodes is electrically connected to one of the third electrodes.

14. The semiconductor device according to claim 8 , wherein
the first semiconductor layer includes a third region between the second region and the second electrode, a concentration of the first conductivity type dopant at the third region is higher than the concentration of the first conductivity type dopant at the second region.

15. The semiconductor device according to claim 1 , wherein
the first region of the first semiconductor layer is in contact with the insulating layer at a bottom of the trench.

16. The semiconductor device according to claim 2 , wherein
the first region of the first semiconductor layer covers the insulating layer at a bottom edge of the trench.

17. The semiconductor device according to claim 1 , wherein
the insulating layer is surrounded by the first region of the first semiconductor layer.

18. The semiconductor device according to claim 1 , wherein
the fourth electrode is electrically connected to the first electrode and insulated from the third electrode.

19. The semiconductor device according to claim 1 , wherein
the first semiconductor layer includes a third region between the second region and the second electrode, a concentration of the first conductivity type dopant at the third region is higher than the concentration of the first conductivity type dopant at the second region.

20. A semiconductor device comprising:
a first semiconductor layer of a first conductivity type;
a second semiconductor layer of a second conductivity type provided on the first semiconductor layer;
a third semiconductor layer of the first conductivity type provided on the second semiconductor layer;
a first electrode electrically connected to the second semiconductor layer and the third semiconductor layer;
a second electrode electrically connected to the first semiconductor layer;
a third electrode embedded in a trench provided through the third semiconductor layer and the second semiconductor layer and into the first semiconductor layer;
a fourth electrode embedded in the trench below the third electrode; and
an insulating layer provided in the trench around the fourth electrode,
wherein the first semiconductor layer includes a first region that is in contact with the insulating layer and at which a concentration of a first conductivity type dopant is lower than the concentration of the first conductivity type dopant at a second region of the first semiconductor layer that is provided around the first region, wherein the first electrode is in contact with the insulating layer at a top of the trench, and wherein an upper surface of the third electrode is below an upper surface of the third semiconductor layer.

Assignees

• Toshiba Kk

Inventors

• Asahara Hidetoshi

Classifications

• H10D64/518

  characterised by their lengths or sectional shapes · CPC title

• H10D62/157

  Impurity concentrations or distributions · CPC title

• H10D30/668

  having trench gate electrodes, e.g. UMOS transistors · CPC title

• H10D64/117 Primary

  Recessed field plates, e.g. trench field plates or buried field plates · CPC title

• H01L29/7813

  Electricity · mapped topic