PCB cavity mode suppression

Patent metadata

Field	Value
Publication number	US-11317502-B2
Application number	US-202016874794-A
Country	US
Kind code	B2
Filing date	May 15, 2020
Priority date	May 15, 2020
Publication date	Apr 26, 2022
Grant date	Apr 26, 2022

Abstract

Methods and apparatus for providing a cavity defined by conductive walls, a printed circuit board (PCB) within the cavity, and shorting posts extending into the cavity to suppress higher order modes generated by operation of the PCB.

First claim

What is claimed is:

1. A system, comprising:
a cavity defined by conductive walls;
a printed circuit board (PCB) within the cavity; and
shorting posts extending into the cavity to suppress higher order modes generated by operation of the PCB,
wherein the shorting posts form a least one edge wall about a perimeter of unit cells of the cavity.

2. The system according to claim 1 , further including a first ground plane layer under the PCB.

3. The system according to claim 2 , further including a second ground plane layer over the PCB, wherein the walls and the first and second ground planes surround the PCB.

4. The system according to claim 1 , wherein the shorting posts comprise solder reflow components.

5. The system according to claim 1 , wherein the shorting posts comprise a series of ball stacks generated from a wire using wire bond equipment.

6. The system according to claim 1 , wherein the shorting posts provide over 30 db mode suppression compared to no shorting posts.

7. The system according to claim 1 , wherein at least one of the edge walls includes a gap in which shorting posts are not located.

8. The system according to claim 7 , further including a shorting post proximate a center of a respective one of the unit cells.

9. The system according to claim 1 , wherein at least some of the shorting posts are located to address point-to-point coupling due to reactive fields.

10. The system according to claim 1 , further including ICs on the PCB and at least some of the shorting posts provide a generally circular formation about the ICs in the cavity.

11. The system according to claim 10 , wherein at least some of the shorting posts are located inside the generally circular formation to reduce coupling between unit cells of the cavity.

12. The system according to claim 10 , wherein shorting posts are spaced from each by about a wavelength of operation for the PCB divided by about five.

13. A method, comprising:
employing a cavity defined by conductive walls;
employing a printed circuit board (PCB) within the cavity; and
employing shorting posts extending into the cavity to suppress higher order modes generated by operation of the PCB,
wherein the shorting posts form a least one edge wall about a perimeter of unit cells of the cavity.

14. The method according to claim 13 , further including employing a first ground plane layer under the PCB.

15. The method according to claim 14 , further including a second ground plane layer over the PCB, wherein the walls and the first and second ground planes surround the PCB.

16. The method according to claim 13 , wherein the shorting posts comprise solder reflow components.

17. The method according to claim 13 , wherein the shorting posts comprise a series of ball stacks generated from a wire using wire bond equipment.

18. The method according to claim 13 , wherein the shorting posts provide over 30 db mode suppression compared to no shorting posts.

Assignees

• Raytheon Co

Inventors

• Sikina Thomas V
• Haven John P
• Benedict James E
• Clark William J
• Favreau Channing P
• Klek Erika
• Pevzner Mikhail
• Hersey Donald G
• Beninati Gregory G
• Tellinghuisen Thomas J

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W44/248

  for antennas · CPC title

• H10W44/216

  Waveguides, e.g. strip lines · CPC title