Semiconductor packages including a bonding wire branch structure

Patent metadata

Field	Value
Publication number	US-11315905-B2
Application number	US-202016910821-A
Country	US
Kind code	B2
Filing date	Jun 24, 2020
Priority date	Jan 10, 2020
Publication date	Apr 26, 2022
Grant date	Apr 26, 2022

Abstract

A semiconductor package includes a package substrate, a die stack having a first sub-stack part and a second sub-stack part, an interface chip, and a bonding wire structure. The bonding wire structure includes a first signal wire connecting first signal die pads included in the first sub-stack part to each other, a first signal extension wire connecting the first signal wire to the interface chip, a second signal wire connecting second signal die pads included in the first sub-stack part to each other, a second signal extension wire connecting the second signal wire to the interface chip, an interpose wire connecting interpose die pads included in the first and second sub-stack parts to each other and electrically connecting the interpose die pads to the interface chip, and a shielding wire branched from the interpose wire.

First claim

What is claimed is:

1. A semiconductor package comprising:
a package substrate;
a die stack configured to include a first sub-stack part stacked on the package substrate and a second sub-stack part disposed between the first sub-stack part and the package substrate, wherein each of the first and second sub-stack parts includes a plurality of semiconductor dies and each of the plurality of semiconductor dies includes a first signal die pad, an interpose die pad, and a second signal die pad;
an interface chip disposed on the package substrate to be spaced apart from the die stack;
a first signal wire connecting the first signal die pads included in the first sub-stack part to each other;
a first signal extension wire extending from the first signal wire to connect the first signal wire to the interface chip;
a second signal wire connecting the second signal die pads included in the first sub-stack part to each other;
a second signal extension wire extending from the second signal wire to connect the second signal wire to the interface chip;
an interpose wire connecting the interpose die pads included in the first and second sub-stack parts to each other and electrically connecting the interpose die pads included in the first and second sub-stack parts to the interface chip; and
a shielding wire branched from the interpose wire to be located between the first and second signal extension wires.

2. The semiconductor package of claim 1 , wherein the shielding wire is branched from the interpose wire and extends to be substantially parallel with the first and second signal extension wires.

3. The semiconductor package of claim 2 , wherein the shielding wire is configured to shield an electromagnetic interference between the first and second signal extension wires by extending to be substantially parallel with the first and second signal extension wires.

4. The semiconductor package of claim 1 ,
wherein the first and second signal extension wires are configured to transmit data signals, and
wherein the shielding wire is configured to supply one of a ground voltage and a power supply voltage.

5. The semiconductor package of claim 1 , wherein the shielding wire is configured to extend in a direction between the first and second signal extension wires and along a same profile as at least one of the first and second signal extension wires.

6. The semiconductor package of claim 1 , further comprising:
a third signal wire connecting the first signal die pads included in the second sub-stack part to each other and extending to electrically connect the first signal die pads included in the second sub-stack part to the interface chip; and
a fourth signal wire connecting the second signal die pads included in the second sub-stack part to each other and extending to electrically connect the second signal die pads included in the second sub-stack part to the interface chip.

7. The semiconductor package of claim 6 ,
wherein the package substrate includes signal bond fingers disposed between the die stack and the interface chip; and
wherein the third and fourth signal wires are bonded to respective ones of the signal bond fingers and are configured to further extend to connect the signal bond fingers to the interface chip.

8. The semiconductor package of claim 7 ,
wherein the package substrate further includes an interpose bond finger disposed between the die stack and the interface chip to be spaced apart from the signal bond fingers; and
wherein the interpose wire is bonded to the interpose bond finger and is configured to further extend to connect the interpose bond finger to the interface chip.

9. The semiconductor package of claim 1 , wherein the shielding wire is branched from the interpose wire on a lowermost semiconductor die of the semiconductor dies included in the first sub-stack part.

10. The semiconductor package of claim 1 , wherein the interpose wire includes:
a first sub-wire, a first ball portion of the first sub-wire is bonded to the interpose die pad located at a position where the shielding wire is branched from the interpose wire; and
a second sub-wire, a stitch portion of which is vertically bonded onto the first ball portion,
wherein the shielding wire includes a second ball portion vertically bonded onto the stitch portion.

11. The semiconductor package of claim 1 , wherein the first and second signal extension wires and the shielding wire extend to be spaced apart from the package substrate and to be connected to the interface chip.

12. The semiconductor package of claim 1 , wherein the interpose die pads are provided as power terminals for applying a power supply voltage to the semiconductor dies.

13. The semiconductor package of claim 1 , wherein the interpose die pads are provided as ground terminals for supplying a ground voltage to the semiconductor dies.

14. The semiconductor package of claim 1 , wherein in each of the semiconductor dies, the interpose die pad is disposed between the first signal die pad and the second signal die pad.

15. The semiconductor package of claim 1 , wherein the interface chip includes chip pads to which the first and second signal extension wires, the interpose wire, and the shielding wire are bonded.

16. A semiconductor package comprising:
a package substrate;
a die stack configured to include a first sub-stack part stacked on the package substrate and a second sub-stack part disposed between the first sub-stack part and the package substrate, wherein each of the first and second sub-stack parts includes a plurality of semiconductor dies and each of the plurality of semiconductor dies includes a first signal die pad, an interpose die pad, and a second signal die pad;
an interface chip disposed on the package substrate to be spaced apart from the die stack and configured to include a first column of chip pads and a second column of chip pads, wherein the first column of chip pads include a first signal chip pad, a shielding chip pad, and a second signal chip pad, and the second column of chip pads include a third signal chip pad, an interpose chip pad, and a fourth signal chip pad;
a first signal wire connecting the first signal die pads included in the first sub-stack part to each other;
a first signal extension wire extending from the first signal wire to connect the first signal wire to the first signal chip pad;
a second signal wire connecting the second signal die pads included in the first sub-stack part to each other;
a second signal extension wire extending from the second signal wire to connect the second signal wire to the second signal chip pad;
an interpose wire connecting the interpose die pads included in the first and second sub-stack parts to each other and electrically connecting the interpose die pads included in the first and second sub-stack parts to the interpose chip pad;
a third signal wire connecting the first signal die pads included in the second sub-stack part to each other and extending to electrically connect the first signal die pads included in the second sub-stack part to the third signal chip pad;
a fourth signal wire connecting the second signal die pads included in the second sub-stack part to each other and extending to electrically connect the second signal die pads included in the second sub-stack part to the fourth signal chip pad; and
a shielding wire branched from the interpose wire to be located between the first and second signal extension wires.

17. The semiconductor package of claim 16 ,
wherein the interface chip includes a first edge and a second edge whi

Assignees

• Sk Hynix Inc

Inventors

• Park Chul

Classifications

• H10W90/752

  between stacked chips · CPC title

• H10W72/50

  Bond wires · CPC title

• H10W20/427

  Power or ground buses · CPC title

• H10W90/24

  at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title