Semiconductor package including stepwise stacked chips

Patent metadata

Field	Value
Publication number	US-10157883-B2
Application number	US-201715404090-A
Country	US
Kind code	B2
Filing date	Jan 11, 2017
Priority date	Jan 16, 2014
Publication date	Dec 18, 2018
Grant date	Dec 18, 2018

Abstract

A semiconductor package comprises a package substrate; a first chip stack and a second chip stack mounted side by side on the package substrate, wherein the first and second chip stacks each include a plurality of semiconductor chips stacked on the package substrate, wherein each of the semiconductor chips includes a plurality of bonding pads provided on a respective edge region thereof, wherein at least some of the plurality of bonding pads are functional pads, and wherein the functional pads occupy a region that is substantially less than an entirety of the respective edge region.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a first chip stack and a second chip stack mounted side by side on a package substrate and each connected to the package substrate in a wire bonding manner,
wherein the first chip stack comprises a plurality of first semiconductor chips that are stepwise stacked on the package substrate to have a descending staircase structure toward the second chip stack,
wherein the second chip stack comprises a plurality of second semiconductor chips that are stepwise stacked on the package substrate to have a descending staircase structure toward the first chip stack,
wherein the first semiconductor chips comprises first pads on first edge regions and second edge regions of top surfaces thereof, respectively,
wherein a pitch of the first pads on the first edge regions is greater than that of the first pads on the second edge regions,
wherein the second semiconductor chips comprising second pads on first edge regions and on second edge regions of top surfaces thereof, respectively,
wherein a pitch of the second pads in the second edge regions is greater than that of the second pads in first edge regions,
wherein the first edge regions of the first semiconductor chips face the first edge regions of the second semiconductor chips in a first direction,
wherein the second edge regions of the first semiconductor chips face the second edge regions of the second semiconductor chips in a second direction crossing the first direction,
wherein the first edge regions of the top surfaces of the first semiconductor chips overlap with a first virtual line in a plan view,
wherein the second edge regions of the top surfaces of the first semiconductor chips overlap with a second virtual line in a plan view, and
wherein the second virtual line is offset from the first virtual line.

2. The package of claim 1 ,
wherein the top surfaces of the first semiconductor chips further comprises third regions, and
wherein the first pads are not provided on the third regions of the top surfaces of the first semiconductor chips.

3. The package of claim 1 , further comprising a third chip disposed on the package substrate between the first chip stack and the second chip stack.

4. The package of claim 3 , further comprising;
first bonding wires connected to one of the first pads and the package substrate; and
second bonding wires connected between the third chip and the package substrate.

5. The package of claim 1 ,
wherein the first pads are electrically connected to integrated circuits of the first semiconductor chips.

6. A semiconductor package, comprising:
a package substrate; and
a first chip stack and a second chip stack mounted side by side on the package substrate and connected to the package substrate via bonding wires, the first chip stack comprises an edge and the second chip stack comprises an edge, the edge of the first chip stack faces the edge of the second chip stack,
wherein the first and second chip stacks include a plurality of semiconductor chips stacked on the package substrate, respectively, the first and second chip stacks have staircase structures that extend away from the edge of the second chip stack and away from the edge of the first chip stack, respectively,
wherein the semiconductor chips include bonding pad groups on first regions of top surfaces thereof and auxiliary pad groups on second regions of the top surfaces thereof, respectively,
wherein each of the bonding pad groups includes bonding pads,
wherein each of the auxiliary pad groups includes auxiliary pads,
wherein pitch of the auxiliary pads is greater than that of the bonding pads,
wherein the bonding pad groups of the first chip stack face the bonding pad groups of the second chip stack in a first direction, and
wherein the auxiliary pad groups of the first chip stack face the auxiliary pad groups of the second chip stack in a second direction crossing the first direction.

7. The semiconductor package of claim 6 ,
wherein the top surfaces of the semiconductor chips further comprising third regions, wherein no pad is provided on the third regions of top surfaces of the semiconductor chips.

8. The semiconductor package of claim 6 ,
wherein the bonding pad groups of the semiconductor chips of the first chip stack are aligned with a first virtual line in a plan view,
wherein the bonding pad groups of the semiconductor chips of the second chip stack are aligned with a second virtual line in a plan view.

9. The semiconductor package of claim 8 ,
wherein first virtual line and the second virtual line are substantially parallel to each other.

10. The semiconductor package of claim 8 ,
wherein the auxiliary pad groups of the semiconductor chips of the first chip stack are aligned with the second virtual line in a plan view.

11. The semiconductor package of claim 8 ,
wherein the auxiliary pad groups of the semiconductor chips of the second chip stack are aligned with the first virtual line in a plan view.

12. The semiconductor package of claim 6 , further comprising one or more third semiconductor chips mounted on the package substrate between the first chip stack and the second chip stack to be electrically coupled to at least one of the first and second chip stacks.

13. The semiconductor package of claim 12 , further comprising substrate bonding wires connected between one of the one or more third semiconductor chips and the package substrate.

14. The semiconductor package of claim 6 ,
wherein the bonding pads and the auxiliary pads are electrically connected to integrated circuits of the semiconductor chips.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Chul
• Kim Kilsoo
• Lee In

Classifications

• H10W90/24

  at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title

• H10W90/271

  the chips having passive surfaces facing each other, i.e. in a back-to-back arrangement · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W72/5445

  being orthogonal to a side surface of the chip, e.g. parallel arrangements · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title