Interrupt signaling for directed interrupt virtualization

Patent metadata

Field	Value
Publication number	US-11314538-B2
Application number	US-202017091498-A
Country	US
Kind code	B2
Filing date	Nov 6, 2020
Priority date	Feb 14, 2019
Publication date	Apr 26, 2022
Grant date	Apr 26, 2022

Abstract

An interrupt signal is provided to a target processor. An interrupt signal is received with an interrupt target ID identifying a processor as a target processor for handling the interrupt signal. The interrupt signal is forwarded to the target processor for handling. A translation of the interrupt target ID to a logical processor ID of the target processor is used to address the target processor directly. The bus attachment device updates a directed interrupt signal indicator of a directed interrupt signal vector assigned to the target processor in order to indicate that there is an interrupt signal addressed to the respective interrupt target ID to be handled.

First claim

What is claimed is:

1. A computer program product for facilitating processing in a computing environment, the computer program product comprising:
at least one computer readable storage medium readable by at least one processing circuit and storing instructions for performing a method comprising:
receiving an interrupt signal with an interrupt target ID, the interrupt target ID identifying one processor of a plurality of processors of the computing environment as a target processor to handle the interrupt signal;
selecting a directed interrupt signal vector assigned to the interrupt target ID to which the interrupt signal is addressed;
selecting, using the directed interrupt signal vector, a directed interrupt signal indicator;
updating the directed interrupt signal indicator such that the directed interrupt signal indicator indicates that there is the interrupt signal addressed to the interrupt target ID to be handled; and
forwarding the interrupt signal to the target processor.

2. The computer program product of claim 1 , wherein the receiving the interrupt signal is from a bus connected module, the bus connected module targeting the interrupt signal to the target processor, and wherein the directed interrupt signal indicator is assigned to the bus connected module which issued the interrupt signal.

3. The computer program product of claim 1 , wherein the receiving the interrupt signal is by a bus attachment device, the bus attachment device to address the target processor directly.

4. The computer program product of claim 3 , wherein the bus attachment device performs the selecting the directed interrupt signal vector, the selecting the directed interrupt signal indicator, the updating and the forwarding.

5. The computer program product of claim 1 , wherein the interrupt signal is associated with an interrupt, and wherein the target processor is selected based on having previously performed one or more activities for the interrupt.

6. The computer program product of claim 1 , wherein the interrupt target ID identifies the one processor of the plurality of processors assigned for usage by a guest operating system as the target processor to handle the interrupt signal.

7. The computer program product of claim 1 , wherein the method further comprises:
retrieving a copy of an interrupt table entry assigned to the interrupt target ID from an interrupt table, the copy of the interrupt table entry comprising a directed interrupt signal vector address indicator indicating a memory address of the directed interrupt signal vector assigned to the interrupt target ID to which the interrupt signal is addressed; and
using the memory address of the directed interrupt signal vector to select the directed interrupt signal vector assigned to the interrupt target ID to which the interrupt signal is addressed.

8. The computer program product of claim 1 , wherein the method further comprises:
selecting from a directed interrupt summary vector a directed interrupt summary indicator assigned to the interrupt target ID to which the interrupt signal is addressed; and
updating the directed interrupt summary indicator such that the directed interrupt summary indicator indicates that there is the interrupt signal addressed to the interrupt target ID to be handled.

9. The computer program product of claim 1 , wherein the method further comprises:
translating the interrupt target ID of the target processor received with the interrupt signal to a logical processor ID of the target processor; and
using the logical processor ID of the target processor to address the target processor as a target of the interrupt signal, when forwarding the interrupt signal to the target processor.

10. The computer program product of claim 1 , wherein the method further comprises:
checking a direct signaling indicator indicating whether the target processor is to be addressed directly;
performing the forwarding, based on the direct signaling indicator indicating a direct forwarding of the interrupt signal, wherein the forwarding uses a logical processor ID of the target processor to address the target processor directly; and
forwarding the interrupt signal using broadcasting, based on the direct signaling indicator not indicating the target processor is to be addressed directly.

11. The computer program product of claim 1 , wherein the method further comprises:
checking a copy of a running indicator indicating whether the target processor identified by the interrupt target ID is scheduled for usage by a guest operating system;
performing the forwarding, based on the target processor being scheduled for usage by the guest operating system, the forwarding comprising forwarding the interrupt signal using a logical processor ID of the target processor to address the target processor directly; and
forwarding the interrupt signal for handling using broadcasting, based on the target processor not being scheduled for usage by the guest operating system.

12. The computer program product of claim 1 , wherein the method further comprises:
checking an interrupt blocking indicator indicating whether the target processor identified by the interrupt target ID is currently blocked from receiving interrupt signals;
performing the forwarding, based on the target processor not being blocked from receiving interrupt signals, the forwarding comprising forwarding the interrupt signal using a logical processor ID of the target processor to address the target processor directly; and
forwarding the interrupt signal using broadcasting, based on the target processor being blocked from receiving interrupt signals.

13. A computer system for facilitating processing in a computing environment, the computer system comprising:
a memory; and
a processor in communication with the memory, wherein the computer system is configured to perform a method, said method comprising:
receiving an interrupt signal with an interrupt target ID, the interrupt target ID identifying one processor of a plurality of processors of the computing environment as a target processor to handle the interrupt signal;
selecting a directed interrupt signal vector assigned to the interrupt target ID to which the interrupt signal is addressed;
selecting, using the directed interrupt signal vector, a directed interrupt signal indicator;
updating the directed interrupt signal indicator such that the directed interrupt signal indicator indicates that there is the interrupt signal addressed to the interrupt target ID to be handled; and
forwarding the interrupt signal to the target processor.

14. The computer system of claim 13 , wherein the receiving the interrupt signal is from a bus connected module, the bus connected module targeting the interrupt signal to the target processor, and wherein the directed interrupt signal indicator is assigned to the bus connected module which issued the interrupt signal.

15. The computer system of claim 13 , wherein the receiving the interrupt signal is by a bus attachment device, the bus attachment device to address the target processor directly.

16. The computer system of claim 13 , wherein the interrupt signal is associated with an interrupt, and wherein the target processor is selected based on having previously performed one or more activities for the interrupt.

17. A computer-implemented method of facilitating processing in a computing environment, the computer-implemented method comprising:
receiving an interrupt signal with an interrupt target ID, the interrupt target ID identifying one processor of a plurality of p

Assignees

• IBM

Inventors

• Raisch Christoph
• Kraemer Marco
• Nerz Bernd
• Schmidt Donald William
• Driever Peter Dana

Classifications

• G06F9/45545 Primary

  Guest-host, i.e. hypervisor is an application program itself, e.g. VirtualBox · CPC title

• G06F9/4812

  by interrupt, e.g. masked · CPC title

• G06F9/542

  Event management; Broadcasting; Multicasting; Notifications · CPC title

• G06F13/24

  using interrupt (G06F13/32 takes precedence) · CPC title

• G06F2009/45579

  I/O management, e.g. providing access to device drivers or storage · CPC title