Error correction methods and apparatuses using first and second decoders

Patent metadata

Field	Value
Publication number	US-10135465-B2
Application number	US-201715434210-A
Country	US
Kind code	B2
Filing date	Feb 16, 2017
Priority date	Nov 8, 2012
Publication date	Nov 20, 2018
Grant date	Nov 20, 2018

Abstract

Apparatuses and methods for error correcting data are provided. A first error correction code (ECC) decoder is configured to decode a first codeword to provide a first result and to decode a second codeword to provide a second result. The decoder is configured to run up to a particular number of iterations to provide each of the results. A second ECC decoder is configured to decode a third codeword to provide decoded data, wherein the third codeword comprises the first result and the second result. An evaluation module is configured to initiate a recovery scheme responsive to the decoded data including an error.

First claim

What is claimed is:

1. A method for error correcting data performed by an apparatus, the method comprising:
using a controller to read a first codeword from memory;
using the controller to read a second codeword from the memory;
decoding the first codeword using a first decoder, without inputting soft data to the first decoder, to yield a first result;
decoding the second codeword using the first decoder, without inputting soft data to the first decoder, to yield a second result;
combining the first result and the second result to form a third codeword;
decoding the third codeword using a second decoder to yield decoded data;
determining, by the second decoder, whether the decoded data includes an error; and
responsive to determining that the decoded data includes an error, performing a recovery scheme comprising:
reading, from the memory, soft data corresponding to the first codeword and soft data corresponding to the second codeword;
providing the soft data corresponding to first codeword and the soft data corresponding to the second codeword to the first decoder only when the decoded third codeword includes the error;
re-decoding the first codeword using the first decoder using the soft data corresponding the first codeword to yield a third result;
re-decoding the second codeword using the first decoder using the soft data corresponding the second codeword to yield a fourth result;
combining the third result and the fourth result to form a fourth codeword; and
decoding the fourth codeword using the second decoder.

2. The method of claim 1 , wherein decoding the first codeword comprises decoding the first codeword with a low density parity check (LDPC) decoder, and wherein decoding the second codeword comprises decoding the second codeword using the LDPC decoder.

3. The method of claim 1 , wherein decoding the third codeword comprises decoding the third codeword using a bit-based decoder.

4. The method of claim 1 , wherein using the controller to read the first and second codewords comprises receiving the first and second codewords at the controller over an interface coupled between the controller and the memory.

5. The method of claim 1 , further comprising:
sensing the first codeword from a first plurality of memory cells of the memory; and
sensing the second codeword from a second plurality of memory cells of the memory.

6. The method of claim 1 , wherein decoding the first and second codeword comprises running the first decoder up to a particular number of iterations to yield the first result and the second result, respectively.

7. The method of claim 1 , wherein decoding the first and second codeword comprises running the first decoder for one iteration to yield the first result and the second result, respectively.

8. An apparatus, comprising:
a first decoder associated with a first error correction code (ECC) decoding procedure and configured to:
decode a plurality of inner codewords without receiving an input of soft data, each of the plurality of inner codewords comprising user data and first ECC bits; and
combine results of decoding the plurality of inner codewords to yield an outer codeword comprising the user data of the plurality of inner codewords and second ECC bits;

a second decoder associated with a second ECC decoding procedure and configured to decode the outer codeword and to use the second ECC bits to correct errors in the user data, wherein the first ECC decoding procedure is different than the second ECC decoding procedure;
wherein the first decoder is further configured to use the first ECC bits to correct errors in the second ECC bits and errors in the user data; and
an evaluation module configured to:
determine whether the decoded outer codeword includes an error; and
responsive to determining that the decoded outer codeword includes an error:
initiate a recovery scheme;
read, from memory, soft data corresponding to the plurality of inner codewords; and
provide the soft data to the first decoder in association with re-decoding the plurality of inner codewords.

9. The apparatus of claim 8 , wherein a number of the first ECC bits is greater than a number of the second ECC bits.

10. The apparatus of claim 8 , wherein the first decoder, the second decoder, and the evaluation module comprise a controller.

11. The apparatus of claim 10 , wherein the controller is configured to read the first and second codewords from the memory while operating in a hard data only mode.

12. The apparatus of claim 8 , wherein the evaluation module is a component of the second decoder.

13. The apparatus of claim 8 , wherein the first decoding procedure is a low density parity check (LDPC) decoding procedure, and
wherein the second decoding procedure is a Reed-Solomon (RS) decoding procedure.

14. A non-transitory computer readable medium storing instructions executable by a processing resource to:
read inner codewords from memory;
decode the inner codewords using a first decoder, without inputting soft data to the first decoder;
combine results from decoding the inner codewords to yield a first outer codeword;
decode the first outer codeword using a second decoder;
determine whether the decoded first codeword includes an error; and
responsive to determining that the decoded first outer codeword includes an error:
read soft data, corresponding to the inner codewords, from the memory;
re-decode the inner codewords using the first decoder using the soft data corresponding to the inner codewords;
combine the re-decoded inner codewords to form a second outer codeword; and
decode the second outer codeword using the second decoder.

15. The medium of claim 14 , further comprising instructions executable to:
determine an error in the outer codeword.

16. The medium of claim 14 , further comprising instructions executable to decode the inner codewords and the outer codeword with a total error correction code (ECC) budget.

17. The medium of claim 14 , further comprising instructions executable to decode the inner codewords serially using the first decoder.

Assignees

• Micron Technology Inc

Inventors

• Parthasarathy Sivagnanam
• Kaynak Mustafa Nazmi
• Khayat Patrick Robert

Classifications

• H03M13/29

  combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes · CPC title

• H03M13/2906

  using block codes (H03M13/2957 takes precedence) · CPC title

• H03M13/152

  Bose-Chaudhuri-Hocquenghem [BCH] codes · CPC title

• G11B20/1833

  by adding special lists or symbols to the coded information (G11B20/1806, G11B20/1866 take precedence) · CPC title

• H03M13/1108 Primary

  Hard decision decoding, e.g. bit flipping, modified or weighted bit flipping · CPC title