Parallel channel skew for enhanced error correction

Patent metadata

Field	Value
Publication number	US-11309995-B2
Application number	US-202016793746-A
Country	US
Kind code	B2
Filing date	Feb 18, 2020
Priority date	Jul 11, 2019
Publication date	Apr 19, 2022
Grant date	Apr 19, 2022

Abstract

Digital communication transmitters, systems, and methods can introduce skew into parallel transmission channels to enhance the performance of forward error correction (FEC) decoders. One illustrative serializer-deserializer (SerDes) transmitter embodiment includes: a block code encoder configured to convert a sequence of input data blocks into a sequence of encoded data blocks; a demultiplexer configured to distribute code symbols from the sequence of encoded data blocks to multiple lanes in a cyclical fashion, the multiple lanes corresponding to parallel transmission channels; a skewer configured to buffer the multiple lanes to provide respective lane delays, the lane delays differing from each other by no less than half an encoded data block period; and multiple drivers, each driver configured to transmit code symbols from one of said multiple lanes on a respective one of said parallel transmission channels.

First claim

What is claimed is:

1. An active cable that comprises electrical conductors joining a first transceiver to a second transceiver to provide parallel transmission channels therebetween, each of the first and second transceivers including:
a block code encoder configured to convert a sequence of input data blocks into a sequence of encoded data blocks;
a demultiplexer configured to distribute code symbols from the sequence of encoded data blocks to multiple lanes in a cyclical fashion;
a skewer configured to buffer the multiple lanes to provide respective lane delays, the lane delays differing from each other by no less than half an encoded data block period; and
multiple drivers each configured to transmit code symbols from one of said multiple lanes on a respective one of said parallel transmission channels.

2. The active cable of claim 1 , wherein each of the first and second transceivers further include:
multiple receivers each configured to convert a receive signal from a respective one of said transmission channels into a sequence of channel symbols;
an alignment module configured to align the multiple sequences of channel symbols using alignment markers to form a sequence of received data blocks; and
a block code decoder configured to convert the received data blocks into a sequence of output data blocks.

3. The active cable of claim 2 , wherein each of the first and second transceivers further includes a deskewer preceding the alignment module, the deskewer being configured to buffer the multiple sequences of channel symbols by predetermined amounts to compensate for the lane delays provided by the skewer.

4. The active cable of claim 1 , wherein the lane delays correspond to integer multiples of an encoded data block period.

5. The active cable of claim 4 , wherein the multiple lanes comprise four lanes.

6. The active cable of claim 1 , wherein the block code encoder is a Reed-Solomon encoder, and the code symbols each comprise 10 bits.

7. The active cable of claim 6 , wherein the multiple drivers each transmit the code symbols as a sequence of NRZ channel symbols.

8. The active cable of claim 6 , wherein the multiple drivers each transmit the code symbols as a sequence of PAM4 channel symbols.

9. A SerDes transmitter that comprises:
a block code encoder configured to convert a sequence of input data blocks into a sequence of encoded data blocks;
a demultiplexer configured to distribute code symbols from the sequence of encoded data blocks to multiple lanes in a cyclical fashion, the multiple lanes corresponding to parallel transmission channels;
a skewer configured to buffer the multiple lanes to provide respective lane delays, the lane delays differing from each other by no less than half an encoded data block period; and
multiple drivers, each driver configured to transmit code symbols from one of said multiple lanes on a respective one of said parallel transmission channels.

10. The transmitter of claim 9 , wherein the block code encoder is a Reed-Solomon encoder, and the code symbols each comprise 10 bits.

11. The transmitter of claim 10 , wherein the multiple drivers each transmit the code symbols as a sequence of NRZ channel symbols.

12. The transmitter of claim 10 , wherein the multiple drivers each transmit the code symbols as a sequence of PAM4 channel symbols.

13. The transmitter of claim 9 , wherein the lane delays correspond to integer multiples of a base delay amount.

14. The transmitter of claim 13 , wherein the base delay amount is an encoded data block period.

15. The transmitter of claim 13 , wherein the multiple lanes comprise four lanes.

16. A digital communication method that comprises:
encoding a sequence of input data blocks into a sequence of encoded data blocks;
distributing the sequence of encoded data blocks in symbol-by-symbol fashion across multiple lanes corresponding to parallel transmission channels;
buffering the multiple lanes to provide respective lane delays, the lane delays differing from each other by no less than half an encoded data block period; and
driving the parallel transmission channels each with symbols from a respective one of the multiple lanes.

17. The method of claim 16 , further comprising:
converting receive signals from the multiple lanes into multiple sequences of channel symbols;
buffering the multiple sequences by predetermined amounts to compensate for said respective lane delays;
using alignment markers to align the multiple sequences to form a sequence of received data blocks; and
decoding the sequence of received data blocks into a sequence of output data blocks.

18. The method of claim 16 , wherein the lane delays correspond to integer multiples of a base delay amount.

19. The method of claim 18 , wherein the base delay amount is an encoded data block period.

20. The method of claim 18 , wherein the multiple lanes comprise four lanes.

Assignees

• Credo Tech Group Ltd

Inventors

• Sun Junqing
• Qian Haoli

Classifications

• H04L1/0041

  Arrangements at the transmitter end · CPC title

• H04L2001/0096

  Channel splitting in point-to-point links · CPC title

• H04L1/0061 Primary

  Error detection codes · CPC title

• H03M9/00

  Parallel/series conversion or vice versa (digital stores in which the information is moved stepwise per se G11C19/00) · CPC title

• H04L25/0272

  Arrangements for coupling to multiple lines, e.g. for differential transmission · CPC title