Gain and memory error estimation in a pipeline analog to digital converter

Patent metadata

Field	Value
Publication number	US-11309902-B2
Application number	US-201916714835-A
Country	US
Kind code	B2
Filing date	Dec 16, 2019
Priority date	Mar 12, 2018
Publication date	Apr 19, 2022
Grant date	Apr 19, 2022

Abstract

In described examples, a stochastic comparator includes a first comparator that compares an input signal and a primary threshold to generate a first signal. A second comparator compares the input signal and the primary threshold to generate a second signal. A decision block generates a control signal in response to the first signal, the second signal and a PRBS (pseudo random binary sequence) signal. A XOR gate generates a detection signal in response the first signal and the second signal.

First claim

What is claimed is:

1. A stochastic comparator comprising:
a first comparator configured to receive an input signal at a positive input terminal and a primary threshold signal at a negative input terminal and generate a first signal;
a second comparator configured to receive the input signal at a positive input terminal and the primary threshold signal at a negative input terminal and generate a second signal; and
a decision block configured to generate a control signal in response to the first signal and the second signal.

2. The stochastic comparator of claim 1 further comprising a XOR gate configured to generate a detection signal in response to the first signal and the second signal, wherein the detection signal is at logic high when the first signal is not equal to the second signal, and the control signal toggles between the ancillary bit and the inverse ancillary bit when the detection signal is at logic high.

3. The stochastic comparator of claim 1 configured to receive a PRBS (pseudo random binary sequence) signal, the PRBS signal comprises a random sequence of binary bits.

4. The stochastic comparator of claim 3 , wherein:
the decision block configured to receive the PRBS (pseudo random binary sequence) signal;
the control signal is equal to one of the first signal and the second signal when the first signal is equal to the second signal;
the control signal is equal to the first signal when the first signal is not equal to the second signal and the PRBS signal is equal to an ancillary bit and
the control signal is equal to the second signal when the first signal is not equal to the second signal and the PRBS signal is equal to an inverse ancillary bit.

5. A pipeline ADC (analog to digital converter) comprising a plurality of stages, and at least one stage comprising:
a flash ADC configured to receive an input signal and configured to generate a flash output;
a DAC (digital to analog converter) coupled to the flash ADC and configured to generate a coarse signal in response to the flash output;
a subtractor coupled to the DAC and configured to generate a residue signal in response to the coarse signal and the input signal; and
a gain amplifier coupled to the subtractor and configured to generate an amplified signal in response to the residue signal, wherein the flash ADC includes one or more stochastic comparators, and each stochastic comparator comprises a first comparator, a second comparator and a decision block, the decision block configured to receive a PRBS (pseudo random binary sequence) signal.

6. The pipeline ADC of claim 4 , wherein in the stochastic comparator:
the first comparator compares the input signal and a primary threshold to generate a first signal;
the second comparator compares the input signal and the primary threshold to generate a second signal; and
the decision block configured to generate a control signal in response to the first signal, the second signal and the PRBS (pseudo random binary sequence) signal.

7. The pipeline ADC of claim 5 , wherein the stochastic comparator further comprises a logic gate, the logic gate is a XOR gate and configured to generate a detection signal in response the first signal and the second signal, and wherein the detection signal is at logic high when the first signal is not equal to the second signal.

8. The pipeline ADC of claim 6 further comprising:
a digital error correction block coupled to the flash ADC of each stage of the plurality of stages, the digital error correction block configured to receive the flash output from each flash ADC and configured to generate a granular signal;
an estimator block configured to generate a correction signal in response to the granular signal, the detection signal and an output of the stochastic comparator; and
a corrector block configured to generate a fine signal in response to the correction signal and the granular signal, wherein the output of the stochastic comparator includes the control signal and the detection signal.

9. The pipeline ADC of claim 7 , wherein the granular signal includes a vestigial output and a digital code.

10. The pipeline ADC of claim 8 , wherein the estimator block is activated when the detection signal is at logic high, and correlates the vestigial output and the control signal to generate the correction signal.

11. The pipeline ADC of claim 8 , wherein the corrector block is configured to correct the digital code based on the correction signal to generate the fine signal.

12. The pipeline ADC of claim 5 , wherein the flash ADC further comprises:
one or more regular comparators configured to compare the input signal and the primary threshold; and
an output block coupled to the one or more regular comparators and to the one or more stochastic comparators, the output block configured to generate the flash output.

13. A method comprising:
comparing an input signal and a primary threshold to generate a first signal, the input signal is received at a positive input terminal and the primary threshold signal is received at a negative input terminal of a first comparator;
comparing the input signal and the primary threshold to generate a second signal, the input signal is received at a positive input terminal and the primary threshold signal is received at a negative input terminal of a second comparator;

and
generating a control signal in response to the first signal and the second signal.

14. The method of claim 13 further comprising generating a detection signal by a XOR gate in response to the first signal and the second signal, wherein the detection signal is at logic high when the first signal is not equal to the second signal, and the control signal toggles between an ancillary bit and an inverse ancillary bit when the detection signal is at logic high.

15. The method of claim 14 further comprising:
receiving a PRBS (pseudo random binary sequence) signal;
generating one of the first signal and the second signal as the control signal when the first signal is equal to the second signal;
generating the first signal as the control signal when the first signal is not equal to the second signal and the PRBS signal is equal to the ancillary bit and
generating the second signal as the control signal when the first signal is not equal to the second signal and the PRBS signal is equal to the inverse ancillary bit.

16. A method of gain error estimation in a pipeline ADC, the pipeline ADC comprising a plurality of stages, comprising:
generating a flash output in response to an input signal by a flash ADC;
generating a coarse signal in response to the flash output;
subtracting the coarse signal from the input signal to generate a residue signal; and
amplifying the residue signal to generate an amplified signal, wherein the flash ADC includes one or more stochastic comparators, and each stochastic comparator configured to receive a PRBS (pseudo random binary sequence) signal and comprises a first comparator, a second comparator and a logic gate.

17. The method of claim 13 further comprising:
comparing the input signal and a primary threshold by the first comparator to generate a first signal; and
comparing the input signal and the primary threshold by the second comparator to generate a second signal.

18. The method of claim 14 further comprising:
generating a control signal in response to the first signal, the second signal and the PRBS (pseudo random binary sequence) signal; and
generating a detection signal by the logic gate in response the first signal and the second sign

Assignees

• Texas Instruments Inc

Inventors

• Naru Srinivas Kumar Reddy
• Rajagopal Narasimhan
• Dusad Shagun
• Nagarajan Viswanathan
• Pentakota Visvesvaraya Appala

Classifications

• H03M1/04

  using stochastic techniques · CPC title

• H03M1/0604 Primary

  at one point, i.e. by adjusting a single reference value, e.g. bias or gain error (gain setting for range control H03M1/18) · CPC title

• H03M1/164

  the steps being performed sequentially in series-connected stages (H03M1/161 takes precedence) · CPC title