Dual-comparator circuit with dynamic VIO shift protection

Patent metadata

Field	Value
Publication number	US-9383393-B2
Application number	US-201414327947-A
Country	US
Kind code	B2
Filing date	Jul 10, 2014
Priority date	Jul 10, 2014
Publication date	Jul 5, 2016
Grant date	Jul 5, 2016

Abstract

A dual-comparator circuit includes a main comparator providing a first decision output (outmain) including a main MOS differential pair, and an auxiliary comparator including an auxiliary MOS differential pair providing a second decision output (outaux). The auxiliary comparator receives a differential input voltage (Vin), and generates a control signal that is coupled to an enable input of the main comparator. A first operating mode (OM) is implemented when |Vin|<a predetermined voltage level (PVL), where the control signal activates the main comparator. A second OM is implemented when |Vin|≧PVL where the main differential pair is protected by a switch from developing transient voltage input offset (VIO). Logic circuitry has logic inputs receiving outaux and outmain, and a logic output providing a decision result for the dual-comparator circuit using outmain when in the first OM and outaux when in the second OM.

First claim

The invention claimed is:

1. A dual-comparator circuit, comprising:
a first comparator (main comparator) including a main metal oxide semiconductor (MOS) differential pair (main MOS differential pair), and an enable input, and a main output providing a first decision output (outmain) when enabled;
a second comparator (auxiliary comparator) including an auxiliary MOS differential pair, wherein said auxiliary comparator is configured to receive a differential input voltage (Vin) and generate a second decision output (outaux) at a control output and a control signal (useaux) at an auxiliary output that is coupled to said enable input of said main comparator;
wherein said dual-comparator circuit is configured to provide a first operating mode [OM] when a magnitude of said Vin is less than (<) a predetermined voltage level (PVL) where said useaux activates said main comparator and said main MOS differential pair receives said Vin, and a second OM implemented when said magnitude of said Vin is greater than or equal to (≧) said PVL wherein said main MOS differential pair is protected by at least one switch from developing transient voltage input offsets (VIO), and
logic circuitry having logic inputs receiving said outaux and said outmain and a logic output providing a decision result for said dual-comparator circuit from said outmain when in said first OM and from said outaux when in said second OM.

2. The dual-comparator circuit of claim 1 , wherein said auxiliary comparator includes circuitry configured for generating at least one flag that indicates whether or not said magnitude of said Vin is ≧said PVL.

3. The dual-comparator circuit of claim 1 , wherein said switch is positioned between high potential nodes of MOS transistors in said main MOS differential pair to always maintain a connection with said Vin to gates of said MOS transistors, and said switch is coupled to receive said useaux.

4. The dual-comparator circuit of claim 1 , wherein said main MOS differential pair includes PMOS transistors.

5. The dual-comparator circuit of claim 1 , further comprising switched current mirror ratio circuitry providing a first current mirror ratio and a second current mirror ratio for providing hysteresis for said dual-comparator circuit.

6. The dual-comparator circuit of claim 2 , wherein said at least one flag comprises a first and a second flag, and wherein said auxiliary comparator includes a Schmitt trigger coupled to receive signals provided at said first and said second flag.

7. The dual-comparator circuit of claim 1 , wherein said PVL is greater than or equal to (≧)|20 mv|.

8. The dual-comparator circuit of claim 1 , wherein said dual-comparator circuit is a component of an analog-to-digital converter (ADC), said ADC comprising:
a digital-to-analog converter (DAC) receiving a reference voltage,
a sample-and hold (S/H) circuit, and
a successive approximation register (SAR) that provides digital signals to said DAC,
wherein said Vin is provided by an output of said S/H circuit and an output of said DAC;
wherein said logic output is coupled to an input of said SAR,
wherein said SAR generates an end-of-conversion (EOC) output for said ADC.

9. The dual-comparator circuit of claim 1 , wherein an ADC is a component of a microcontroller unit (MCU), said MCU comprising:
a first non-volatile program memory;
a volatile data memory;
a digital I/O (interface);
a central processing unit (CPU);
a clock, and
a digital data bus and an address bus for coupling together said first non-volatile program memory, said volatile data memory, said digital I/O (interface), said CPU, and said clock.

10. A method of comparing an input voltage (Vin) to a predetermined voltage level (PVL), comprising:
providing a dual-comparator circuit including a first comparator (main comparator) including a main metal oxide semiconductor (MOS) differential pair (main MOS differential pair), and an enable input, and providing a first decision output (outmain) when enabled, and a second comparator (auxiliary comparator) including an auxiliary MOS differential pair generating a second decision output (outaux) at a control output,
at least said auxiliary comparator receiving said Vin;
implementing a first operating mode (OM) when a magnitude of said Vin is less than (<) said PVL with said auxiliary comparator activating said main comparator where said main MOS differential pair receives said Vin, and using said outmain as a decision result for said dual-comparator circuit, and
implementing a second OM used when said magnitude of said Vin is greater than or equal to (≧) said PVL, and using said outaux for said decision result for said dual-comparator circuit while protecting said main MOS differential pair from developing transient voltage offsets by switching a switch.

11. The method of claim 10 , wherein said auxiliary comparator further generates a control signal (useaux) at an auxiliary output that is coupled to said enable input of said main comparator.

12. The method of claim 10 , wherein said switching reduces a difference in high potential node-to-gate voltage between respective MOS transistors in said main MOS differential pair.

13. The method of claim 10 , wherein said auxiliary comparator further generates at least one flag that indicates whether or not said magnitude of said Vin is ≧said PVL.

14. The method of claim 11 , wherein said switch is positioned between high potential nodes of MOS transistors in said main MOS differential pair to always maintain a connection with said Vin to gates of said MOS transistors, and said switch is coupled to receive said useaux.

15. The method of claim 10 , wherein said main MOS differential pair includes PMOS transistors.

16. The method of claim 10 , further comprising switching a current mirror ratio between a first current mirror ratio and a second current mirror ratio for providing hysteresis for said dual-comparator circuit.

17. The method of claim 13 , wherein said at least one flag comprises a first and a second flag, and wherein said auxiliary comparator includes a Schmitt trigger coupled to receive signals at said first and said second flag.

18. The method of claim 10 , wherein said PVL is greater than or equal to ≧20 mV.

19. The method of claim 10 , wherein an external circuit determines whether said magnitude of said Vin is <said PVL or is ≧said PVL.

Assignees

• Texas Instruments Deutschland

Inventors

• Gerber Johannes
• Ruck Bernhard
• Qaiyum Asif
• Kuhn Ruediger

Classifications

• G01R19/16576 Primary

  comparing DC or AC voltage with one threshold (G01R19/16514, G01R19/16519, G01R19/16528, G01R19/16533 and G01R19/1659 take precedence) · CPC title

• H03M1/46

  with digital/analogue converter for supplying reference values to converter · CPC title

• H03M1/1245

  Details of sampling arrangements or methods · CPC title