Compact and efficient CMOS inverter

Patent metadata

Field	Value
Publication number	US-11302586-B2
Application number	US-202016836590-A
Country	US
Kind code	B2
Filing date	Mar 31, 2020
Priority date	Mar 31, 2020
Publication date	Apr 12, 2022
Grant date	Apr 12, 2022

Abstract

A structure for providing an inverter circuit employing two vertical transistor structures formed on a semiconductor substrate. The vertical semiconductor structures each include a semiconductor pillar structure and a surrounding gate dielectric. A gate structure is formed to at least partially surround the first and second vertical transistor structures. The semiconductor substrate is formed into first and section regions that are separated by a dielectric isolation structure. The first region includes a P+ doped portion and an N+ doped portion, and the second region includes an N+ doped portion and a P+ doped portion. The N+ and P+ doped portions of the first and second regions can be arranged such that the N+ doped portion of the first region is adjacent to the P+ doped portion of the second region, and the P+ doped portion of the first region is adjacent to the N+ doped portion of the second region.

First claim

What is claimed is:

1. An inverter structure comprising:
a semiconductor substrate;
first and second regions formed in the semiconductor substrate, the first and second regions being separated by a dielectric isolation structure, the first region having an N+ doped portion and a P+ doped portion on a surface of the semiconductor substrate and the second region having a P+ doped portion and an N+ doped portion on the surface of the semiconductor substrate, wherein the N+ doped portion and the P+ doped portion in each of the first region and second region are adjacent to each other without an overlay between each other, the P+ doped portion of the first region is adjacent to the N+ doped portion of the second region along a direction perpendicular to an alignment of the P+ doped portion and N+ doped portion in the first region, and the N+ doped portion of the first region is adjacent to the P+ doped portion of the second region along a same direction;
a first vertical transistor structure formed on the P+ doped portion of the first region of the semiconductor substrate, and a second vertical transistor structure formed on the N+ doped portion of the second region of the semiconductor substrate;
wherein the first and second vertical transistor structures each comprise a semiconductor pillar structure, at least a portion of which is substantially monocrystalline, and a gate dielectric layer surrounding the semiconductor pillar structure, and further comprising a gate structure at least partially surrounding the gate dielectric layer of each of the first and second vertical transistor structures; and
wherein the inverter structure further comprises a first electrically conductive lead connected with the semiconductor pillar structure of each of the first and second transistor structures, a second electrically conductive lead electrically connected with the N+ doped portion and P+ doped portion of the first region of the semiconductor substrate, and a third electrically conductive lead electrically connected with the N+ doped portion and P+ doped portion of the second region.

2. The inverter structure as in claim 1 , wherein the gate structure includes a layer of electrically conductive material located between first and second dielectric layers.

3. The inverter structure as in claim 1 , wherein the semiconductor pillar structures of each of the vertical transistor structures comprises an epitaxially grown semiconductor material.

4. The inverter structure as in claim 1 , wherein the semiconductor pillar structure of each of the vertical transistor structures is at least 80 percent monocrystalline by volume.

5. The inverter structure as in claim 1 , wherein the semiconductor pillar structure of each of the vertical transistor structures is at least 90 percent monocrystalline by volume.

6. The inverter structure as in claim 1 , wherein each of the semiconductor pillar structures has a rectangular prism shape.

Assignees

• Integrated Silicon Solution Cayman Inc

Inventors

• Levi Amitay
• Beery Dafna
• Walker Andrew J

Classifications

• H10P50/691

  for Group V materials or Group III-V materials · CPC title

• H10P50/242

  of Group IV materials · CPC title

• H10P14/27

  using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10D84/85

  Complementary IGFETs, e.g. CMOS · CPC title