Apparatus and method for dynamic control of microprocessor configuration

Patent metadata

Field	Value
Publication number	US-11301298-B2
Application number	US-202016833595-A
Country	US
Kind code	B2
Filing date	Mar 28, 2020
Priority date	Mar 28, 2020
Publication date	Apr 12, 2022
Grant date	Apr 12, 2022

Abstract

An apparatus and method for intelligently scheduling threads across a plurality of logical processors. For example, one embodiment of a processor comprises: a plurality of cores to be allocated to form a first plurality of logical processors (LPs) to execute threads, wherein one or more logical processors (LPs) are to be associated with each core of the plurality of cores; scheduling guide circuitry to: monitor execution characteristics of the first plurality of LPs and the threads; generate a first plurality of LP rankings, each LP ranking including all or a subset of the plurality of LPs in a particular order; and store the first plurality of LP rankings in a memory to be provided to a scheduler, the scheduler to schedule the threads on the plurality of LPs using the first plurality of LP rankings; a power controller to execute power management code to perform power management operations including independently adjusting frequencies and/or voltages of one or more of the plurality of cores; wherein in response to a core configuration command to deactivate a first core of the plurality of cores, the power controller or privileged program code executed on the processor are to update the memory with an indication of deactivation of the first core, wherein responsive to the indication of deactivation of the first core, the scheduler is to modify the scheduling of the threads.

First claim

What is claimed is:

1. A processor comprising:
a plurality of cores to be allocated to form a first plurality of logical processors (LPs) to execute threads, wherein one or more logical processors (LPs) are to be associated with each core of the plurality of cores;
scheduling guide circuitry to:
monitor execution characteristics of the first plurality of LPs and the threads;
generate a first plurality of LP rankings, each LP ranking including all or a subset of the plurality of LPs in a particular order; and
store the first plurality of LP rankings in a memory to be provided to a scheduler, the scheduler to schedule the threads on the plurality of LPs using the first plurality of LP rankings;

a power controller to execute power management code to perform power management operations including independently adjusting frequencies and/or voltages of one or more of the plurality of cores;
wherein in response to a core configuration command to deactivate a first core of the plurality of cores, the power controller or privileged program code executed on the processor are to update the memory with an indication of deactivation of the first core,
wherein responsive to the indication of deactivation of the first core, the scheduler is to modify the scheduling of the threads.

2. The processor of claim 1 wherein responsive to the indication of deactivation of the core, the scheduling guide circuitry is to generate a second plurality of LP rankings which either do not include one or more LPs associated with the first core or which rank the one or more LPs associated with the first core lower than any other LPs of the first plurality of LPs.

3. The processor of claim 2 wherein the privileged program code comprises a management driver, the management driver to update the memory with an indication of deactivation of the first core.

4. The processor of claim 1 wherein responsive to the core configuration command, the power controller is to set a frequency and/or voltage restriction for the first core of the plurality of cores.

5. The processor of claim 4 wherein the power controller is to generate an interrupt to the scheduler to notify the scheduler to read the indication of deactivation of the first core from the memory.

6. The processor of claim 5 wherein the scheduler comprises an operating system (OS) scheduler.

7. The processor of claim 1 wherein the core configuration command is generated by a management agent executed on the processor.

8. The processor of claim 7 wherein the privileged program code comprises a management driver to forward the core configuration command to the power controller.

9. A method comprising:
associating a first plurality of logical processors (LPs) with a plurality of cores, the LPs to execute a plurality of threads;
monitoring execution characteristics of the first plurality of LPs and the threads;
generating first plurality of LP rankings, each LP ranking including all or a subset of the plurality of LPs in a particular order; and
storing the first plurality of LP rankings in a memory to be provided to a scheduler;
scheduling the threads on the plurality of LPs using the first plurality of LP rankings;
executing power management code to perform power management operations including independently adjusting frequencies and/or voltages of one or more of the plurality of cores;
wherein in response to a core configuration command to deactivate a first core of the plurality of cores, updating the memory with an indication of deactivation of the first core,
wherein responsive to the indication of deactivation of the first core, modifying the scheduling of the threads.

10. The method of claim 9 wherein responsive to the indication of deactivation of the core, a second plurality of LP rankings is generated either not to include one or more LPs associated with the first core or to rank the one or more LPs associated with the first core lower than any other LPs of the first plurality of LPs.

11. The method of claim 10 wherein the updating the memory with the indication of deactivation of the first core is performed by a management driver.

12. The method of claim 9 wherein responsive to the core configuration command, the power controller is to set a frequency and/or voltage restriction for the first core of the plurality of cores.

13. The method of claim 12 wherein the power controller is to generate an interrupt to the scheduler to notify the scheduler to read the indication of deactivation of the first core from the memory.

14. The method of claim 13 wherein the scheduler comprises an operating system (OS) scheduler.

15. The method of claim 9 wherein the core configuration command is generated by a management agent executed on one or more of the cores.

16. The method of claim 15 wherein the core configuration command is forwarded to the power controller by a management driver.

17. A non-transitory machine-readable medium having program code stored thereon which, when executed by a machine, causes the machine to perform the operations of:
associating a first plurality of logical processors (LPs) with a plurality of cores, the LPs to execute a plurality of threads;
monitoring execution characteristics of the first plurality of LPs and the threads;
generating first plurality of LP rankings, each LP ranking including all or a subset of the plurality of LPs in a particular order; and
storing the first plurality of LP rankings in a memory to be provided to a scheduler;
scheduling the threads on the plurality of LPs using the first plurality of LP rankings;
executing power management code to perform power management operations including independently adjusting frequencies and/or voltages of one or more of the plurality of cores;
wherein in response to a core configuration command to deactivate a first core of the plurality of cores, updating the memory with an indication of deactivation of the first core,
wherein responsive to the indication of deactivation of the first core, modifying the scheduling of the threads.

18. The non-transitory machine-readable medium of claim 17 wherein responsive to the indication of deactivation of the core, a second plurality of LP rankings is generated either not to include one or more LPs associated with the first core or to rank the one or more LPs associated with the first core lower than any other LPs of the first plurality of LPs.

19. The non-transitory machine-readable medium of claim 18 wherein the updating the memory with the indication of deactivation of the first core is performed by a management driver.

20. The non-transitory machine-readable medium of claim 17 wherein responsive to the core configuration command, the power controller is to set a frequency and/or voltage restriction for the first core of the plurality of cores.

21. The non-transitory machine-readable medium of claim 20 wherein the power controller is to generate an interrupt to the scheduler to notify the scheduler to read the indication of deactivation of the first core from the memory.

22. The non-transitory machine-readable medium of claim 21 wherein the scheduler comprises an operating system (OS) scheduler.

23. The non-transitory machine-readable medium of claim 20 wherein the core configuration command is generated by a management agent executed on one or more of the cores.

24. The non-transitory machine-readable medium of claim 23 wherein the core configuration command is

Assignees

• Intel Corp

Inventors

• Varma Ankush
• Gupta Nikhil
• Srinivasan Vasudevan
• Sistla Krishnakanth
• Palit Nilanjan
• Karhu Abhinav
• Gorbatov Eugene
• Weissmann Eliezer

Classifications

• G06F1/329

  by task scheduling · CPC title

• G06F9/5038 Primary

  considering the execution order of a plurality of tasks, e.g. taking priority or time dependency constraints into consideration (scheduling strategies G06F9/4881 and subgroups) · CPC title

• G06F2209/5018

  Thread allocation · CPC title

• G06F2209/484

  Precedence · CPC title

• G06F2209/5021

  Priority · CPC title