Systems and methods for testing jitter tolerance

Patent metadata

Field	Value
Publication number	US-11300613-B2
Application number	US-202017022311-A
Country	US
Kind code	B2
Filing date	Sep 16, 2020
Priority date	Sep 16, 2020
Publication date	Apr 12, 2022
Grant date	Apr 12, 2022

Abstract

A method of assessing the ability of one or more multi-die circuit elements to tolerate the presence of jitter in intra-package. The method includes: providing a first die having a set of transmitters for digital communications, the set of transmitters comprising a first transmitter and a second transmitter; providing a second die having a set of receivers for digital communications; providing a performance monitor; coupling, using an intra-package trace, a first transmit signal from the first transmitter to a receiver of the set of receivers; coupling a second transmit signal from the second transmitter to an external pin; supplying an input signal that induces jitter in the first and second transmit signals; measuring jitter in the second transmit signal via the external pin; and determining, using the performance monitor, a performance characteristic of the second die.

First claim

It is claimed:

1. A jitter tolerance testing method that comprises:
providing a first die having a set of transmitters for digital communications, the set of transmitters comprising a first transmitter and a second transmitter;
providing a second die having a set of receivers for digital communications, at least one of the receivers comprising a performance monitor;
coupling, using an intra-package trace, a first transmit signal from the first transmitter to a receiver of the set of receivers;
coupling a second transmit signal from the second transmitter to an external pin;
supplying an input signal that induces jitter in the first and second transmit signals;
measuring jitter in the second transmit signal via the external pin; and
determining, using the performance monitor, a performance characteristic of the second die.

2. The jitter tolerance testing method of claim 1 , wherein the input signal is a reference signal with controllable sinusoidal jitter, and the first die includes a phase lock loop that converts the reference signal into a symbol clock signal for the first transmitter and the second transmitter.

3. The jitter tolerance testing method of claim 1 , wherein the input signal is a reference signal with controllable sinusoidal jitter, and the first die includes a first phase lock loop that converts the reference signal into a first symbol clock signal for the first transmitter and a second phase lock loop that converts the reference signal into a second symbol clock signal for the second transmitter, wherein the first phase lock loop and the second phase lock loop are configured to introduce equivalent jitter in the first symbol clock signal and the second symbol clock signal.

4. The jitter tolerance testing method of claim 1 , wherein the input signal is a phase control signal for a phase rotator that operates on output of a transmitter phase lock loop to modify a phase of a sample clock signal for the first and second transmitters.

5. The jitter tolerance testing method of claim 1 , wherein the input signal is a phase control signal for a first phase rotator that operates to modify a phase of a first sample clock signal for the first transmitter and wherein the input signal is a phase control signal for a second phase rotator that operates to modify a phase of a second sample clock signal for the second transmitter, wherein the first phase rotator and the second phase rotator are configured to introduce equivalent jitter in the first sample clock signal and the second sample clock signal.

6. The jitter tolerance testing method of claim 1 , wherein the input signal is a divider control signal for a multi-modulus divider in a first phase lock loop that converts a reference signal into a symbol clock signal for the first transmitter and the second transmitter.

7. The jitter tolerance testing method of claim 1 , wherein the input signal is a divider control signal for a first multi-modulus divider in a first phase lock loop and a second multi-modulus divider in a second phase lock loop, wherein the first multi-modulus divider converts a reference signal into a first symbol clock signal for the first transmitter, and the second multi-modulus divider converts the reference signal into a second symbol clock signal for the second transmitter, wherein the first phase lock loop and the second phase lock loop are configured to introduce equivalent jitter in the first symbol clock signal and the second symbol clock signal.

8. The jitter tolerance testing method of claim 1 , wherein the input signal is a phase control signal for a phase rotator in a feedback path of a first phase lock loop that converts a reference signal into a symbol clock signal for the first and second transmitters.

9. The jitter tolerance testing method of claim 1 , wherein the input signal is a phase control signal for a first phase rotator in a first feedback path of a first phase lock loop and a second phase rotator in a second feedback path of a second phase lock loop, wherein the first phase rotator converts a reference signal into a first symbol clock signal for the first transmitter, and the second phase lock loop converts the reference signal into a second symbol clock signal for the second transmitter.

10. The jitter tolerance testing method of claim 1 , wherein the jitter has a sinusoidal phase variation with an amplitude and frequency, and wherein measuring jitter in the second transmit signal via the external pin includes determining the amplitude and the frequency of a sinusoidal phase variation associated with controllable parameters of the input signal.

11. The jitter tolerance testing method of claim 10 , further comprising determining a dependence of a performance characteristic of one or more receivers on at least one of the amplitude or frequency associated with controllable parameters of the input signal.

12. The jitter tolerance testing method of claim 1 , further comprising determining amplitude and frequency values at which a performance characteristic of one or more receivers crosses a predefined threshold, wherein the performance characteristic is one of bit error rate, symbol error rate, or mean square error rate.

13. A jitter tolerance testing system that comprises:
a package; and
a test controller,
the package including:
a first die having a first transmitter and a second transmitter;
a second die having a receiver and a performance monitor;
a signal path coupling a first transmit signal from the first transmitter to the receiver; and
an external pin making a second transmit signal from the second transmitter available to the test controller, and

the test controller including:
a signal generator that supplies an input signal to the package to induce jitter in the first and second transmit signals;
a jitter measurement circuit that measures jitter in the second transmit signal; and
a processor that controls the input signal, obtains the measured jitter from jitter measurement circuit, and obtains a performance indicator signal from the performance monitor, the performance indicator signal indicative of an ability of one or more components of the second die to retrieve data from the first transmit signal despite the jitter.

14. The jitter tolerance testing system of claim 13 , wherein the signal path coupling the first transmit signal from the first transmitter to the receiver comprises an intra-package trace.

15. The jitter tolerance testing system of claim 13 , wherein the input signal is a reference signal with controllable sinusoidal jitter, and the first die includes a phase lock loop that converts the reference signal into a symbol clock signal for the first transmitter and the second transmitter.

16. The jitter tolerance testing system of claim 13 , wherein the input signal is a reference signal with controllable sinusoidal jitter, and the first die includes a first phase lock loop that converts the reference signal into a first symbol clock signal for the first transmitter and a second phase lock loop that converts the reference signal into a second symbol clock signal for the second transmitter.

17. The jitter tolerance testing system of claim 13 , the package further including a phase rotator and a sample clock signal generator that generates a sample clock signal, and wherein the input signal is a phase control signal for the phase rotator that operates to modify a phase of the sample clock signal for the first and second transmitters.

18. The jitter tolerance testing system of claim 13 , the package further including a first phase rota

Assignees

• Credo Tech Group Ltd

Inventors

• Aga Arshan
• Qian Haoli
• Sun Junqing
• Bartenslager James

Classifications

• G01R31/318513

  Test of Multi-Chip-Moduls · CPC title

• G01R31/31709 Primary

  Jitter measurements; Jitter generators (measuring jitter, noise figure or signal-to-noise ratio per se G01R29/26; analysis of tester signals G01R31/31901) · CPC title

• G01R29/26

  Measuring noise figure; Measuring signal-to-noise ratio · CPC title