Power transistor with distributed gate

Patent metadata

Field	Value
Publication number	US-11296601-B2
Application number	US-202016813733-A
Country	US
Kind code	B2
Filing date	Mar 9, 2020
Priority date	Aug 20, 2014
Publication date	Apr 5, 2022
Grant date	Apr 5, 2022

Abstract

An electronic circuit is disclosed. The electronic circuit includes a distributed power switch. In some embodiments, the electronic circuit also includes one or more of a distributed gate driver, a distributed gate pulldown device, a distributed diode, and a low resistance gate and/or source connection structure. An electronic component comprising the circuit, and methods of manufacturing the circuit are also disclosed.

First claim

What is claimed is:

1. An electronic circuit, comprising:
a substrate comprising GaN;
a distributed GaN power switch formed on the substrate and including a plurality of power sub-transistors that each comprise a respective first gate, a respective first source, and a respective first drain;
wherein each respective first gate of each of the plurality of power sub-transistors is electrically connected to the respective first gate of each of the other power sub-transistors of the plurality of power sub-transistors at a common power gate node;
wherein each respective first source of each of the plurality of power sub-transistors is electrically connected to the respective first source of each of the other power sub-transistors of the plurality of power sub-transistors at a common power source node; and
wherein each respective first drain of each of the plurality of power sub-transistors is electrically connected to the respective first drain of each of the other power sub-transistors of the plurality of power sub-transistors at a common power drain node; and

a distributed GaN pull-down switch formed on the substrate and including a plurality of pull-down sub-transistors that each comprise a respective second gate, a respective second source, and a respective second drain;
wherein each respective second gate of each of the plurality of pull-down sub-transistors is electrically connected to the respective second gate of each of the other pull-down sub-transistors of the plurality of pull-down sub-transistors at a common pull-down gate node;
wherein each respective second source of each of the plurality of pull-down sub-transistors is electrically connected to the respective second source of each of the other pull-down sub-transistors of the plurality of pull-down sub-transistors at a common pull-down source node; and
wherein each respective second drain of each of the plurality of pull-down sub-transistors is electrically connected to the respective second drain of each of the other pull-down sub-transistors of the plurality of pull-down sub-transistors at the common power gate node;

wherein each pull-down sub-transistor of the plurality of pull-down sub-transistors is physically adjacent a respective one of the power sub-transistors of the plurality of power sub-transistors;
wherein each respective second gate of each of the plurality of pull-down sub-transistors is electrically connected to a first driver circuit that controls operation of the distributed GaN pull-down switch between an on state and an off state, wherein when in the on state the distributed GaN pull-down switch couples the power gate node to the pull-down source node causing the distributed GaN power switch to be in an off state such that the power drain node is electrically isolated from the power source node;
wherein each respective first gate of each of the plurality of power sub-transistors is electrically connected to a second driver circuit that controls operation of the distributed GaN power switch between an on state and an off state, wherein when in the on state the power drain node is connected to the power source node and when in the off state the power drain node is electrically isolated from the power source node.

2. The electronic circuit of claim 1 , wherein each power sub-transistor of the plurality of power sub-transistors is physically adjacent a respective one of the pull-down sub-transistors of the plurality of pull-down sub-transistors.

3. The electronic circuit of claim 1 , further comprising an interconnect structure between the plurality of power sub-transistors and the plurality of pull-down sub-transistors, wherein the interconnect structure is configured to electrically connect each respective first gate of each of the plurality of power sub-transistors to other respective first gates of the other power sub-transistors.

4. The electronic circuit of claim 1 , further comprising an interconnect structure between the plurality of power sub-transistors and the plurality of pull-down sub-transistors, wherein the interconnect structure is configured to electrically connect each respective first gate of each of the plurality of power sub-transistors to each respective second drain of each of the pull-down sub-transistors of the plurality of pull-down sub-transistors.

5. The electronic circuit of claim 1 , further comprising an interconnect structure between the plurality of power sub-transistors and the plurality of pull-down sub-transistors, wherein the interconnect structure is configured to electrically connect each respective first source of each of the plurality of power sub-transistors to each respective second source of each of the pull-down sub-transistors of the plurality of pull-down sub-transistors.

6. The electronic circuit of claim 1 , wherein each of the plurality of power sub-transistors has an identical orientation as the other each of the plurality of power sub-transistors with respect to the substrate.

7. The electronic circuit of claim 1 , wherein each of the plurality of pull-down sub-transistors has an identical orientation as the other each of the plurality of pull-down sub-transistors with respect to the substrate.

8. The electronic circuit of claim 1 , further comprising:
a GaN power switch formed on the substrate, wherein a source terminal of the GaN power switch is connected to the common power drain node of the distributed GaN power switch; and
a GaN pull-down switch formed on the substrate.

9. An electronic circuit, comprising:
a substrate comprising GaN;
a first distributed GaN power switch formed on the substrate and including a plurality of first power sub-transistors that each comprise a respective first gate, a respective first source, and a respective first drain;
wherein each respective first gate of each of the plurality of first power sub-transistors is electrically connected to the respective first gate of each of the other first power sub-transistors of the plurality of first power sub-transistors at a common first power gate node;
wherein each respective first source of each of the plurality of first power sub-transistors is electrically connected to the respective first source of each of the other first power sub-transistors of the plurality of first power sub-transistors at a common power source node; and
wherein each respective first drain of each of the plurality of first power sub-transistors is electrically connected to the respective first drain of each of the other first power sub-transistors of the plurality of first power sub-transistors at a common first power drain node; and

a first distributed GaN pull-down switch formed on the substrate and including a plurality of first pull-down sub-transistors that each comprise a respective second gate, a respective second source, and a respective second drain;
wherein each respective second gate of each first of the plurality of pull-down sub-transistors is electrically connected to the respective second gate of each of the other first pull-down sub-transistors of the plurality of first pull-down sub-transistors at a common first pull-down gate node;
wherein each respective second source of each first of the plurality of pull-down sub-transistors is electrically connected to the respective second source of each of the other first pull-down sub-transistors of the plurality of first pull-down sub-transistors at a common first pull-down source node; and
wherein each respective second drain of each first of the plurality of pull-down sub-transistors is electrically connected to the respective second drain of each of the other first pull-down sub-transistors of the plurality of first pull-down sub-transistors at the common first power gate node of the f

Assignees

• Navitas Semiconductor Inc
• Navitas Semiconductor Ltd

Inventors

• Kinzer Daniel M

Classifications

• H10W20/484

  Interconnections having extended contours, e.g. pads having mesh shape or interconnections comprising connected parallel stripes · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10D84/83

  of only insulated-gate FETs [IGFET] · CPC title

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title