Electrostatic discharge protection circuits and semiconductor circuits

Patent metadata

Field	Value
Publication number	US-11296503-B1
Application number	US-202017136485-A
Country	US
Kind code	B1
Filing date	Dec 29, 2020
Priority date	Dec 29, 2020
Publication date	Apr 5, 2022
Grant date	Apr 5, 2022

Abstract

An electrostatic discharge protection (ESD) circuit is provided for a semiconductor element. The semiconductor element includes first and second drain/source electrodes and is surrounded by a deep well region. The ESD circuit includes a first control circuit and a first discharge circuit. The first control circuit is electrically connected between the first drain/source electrode and a power terminal and includes a first control terminal electrically connected to the deep well region and generates a first control signal. The first discharge circuit is controlled by the first control signal. When an electrostatic discharge event occurs on the first drain/source electrode, the first control circuit generates the first control signal according to potential states of the deep well region and the first drain/source electrode, and the first discharge circuit provides a first discharge path between the first drain/source electrode and the power terminal according to the first control signal.

First claim

What is claimed is:

1. An electrostatic discharge protection circuit for a semiconductor element, the semiconductor element comprising a first drain/source electrode and a second drain/source electrode and surrounded by a deep well region, the electrostatic discharge protection circuit comprising:
a first control circuit electrically connected between the first drain/source electrode of the semiconductor element and a power terminal and comprising a first control terminal, wherein the first control terminal is electrically connected to the deep well region, and the first control circuit generates a first control signal; and
a first discharge circuit electrically connected between the first drain/source electrode and the power terminal and controlled by the first control signal,
wherein when an electrostatic discharge event occurs on the first drain/source electrode, the first control circuit generates the first control signal according to a potential state of the deep well region and a potential state of the first drain/source electrode, and the first discharge circuit provides a first discharge path between the first drain/source electrode and the power terminal according to the first control signal.

2. The electrostatic discharge protection circuit as claimed in claim 1 , wherein the first control circuit comprises:
a first inverter electrically connected between the first drain/source electrode and the power terminal and comprising a first input terminal and a first output terminal,
wherein the first input terminal is electrically connected to the first control terminal, and
wherein the first inverter selectively uses the potential state of the first drain/source electrode or a potential state of the power terminal based on the potential state of the deep well region to determine a voltage of the first output terminal, and the first control circuit generates the first control signal according to the voltage of the first output terminal.

3. The electrostatic discharge protection circuit as claimed in claim 2 , wherein when an electrostatic discharge event occurs on the first drain/source electrode, the first inverter generates the first control signal according to the potential state of the first drain/source electrode.

4. The electrostatic discharge protection circuit as claimed in claim 3 wherein the electrostatic discharge event occurs during a period when the potential state of the deep well region is a floating state.

5. The electrostatic discharge protection circuit as claimed in claim 2 , wherein when the semiconductor element is in a normal operation mode, the first inverter generates the first control signal according to the potential state of the power terminal to control the discharge circuit to cut off the first discharge path.

6. The electrostatic discharge protection circuit as claimed in claim 5 , wherein in the normal operation mode, the deep well region receives an operation voltage.

7. The electrostatic discharge protection circuit as claimed in claim 2 , wherein the first inverter comprises:
a first P-type transistor having a control electrode electrically connected to the first input terminal, a first electrode electrically connected to the first drain/source electrode, and a second electrode electrically connected to the first output terminal; and
a first N-type transistor having a control electrode electrically connected to the first input terminal, a first electrode electrically connected to the first output terminal, and a second electrode electrically connected to the power terminal.

8. The electrostatic discharge protection circuit as claimed in claim 7 , wherein the first discharge circuit comprises:
a second N-type transistor having a control electrode electrically connected to the first output terminal, a first electrode electrically connected to the first drain/source electrode, and a second electrode electrically connected to the power terminal.

9. The electrostatic discharge protection circuit as claimed in claim 2 , wherein the first control circuit further comprises:
a second inverter electrically connected to the first drain/source electrode and the power terminal and comprising a second input terminal and a second output terminal,
wherein the second input terminal is electrically connected to the first output terminal, and
wherein the second inverter selectively uses the potential state of the first drain/source electrode or the potential state of the power terminal based on the voltage of the first output terminal to generate the first control signal.

10. The electrostatic discharge protection circuit as claimed in claim 1 , further comprising:
a second control circuit electrically connected between the second drain/source electrode of the semiconductor element and the power terminal and comprising a second control terminal, wherein the second control terminal is electrically connected to the deep well region, and the second control circuit generates a second control signal; and
a second discharge circuit electrically connected between the second drain/source electrode and the power terminal and controlled by the second control signal,
wherein when the electrostatic discharge event occurs on the second drain/source electrode, the second control circuit generates the second control signal according to the potential state of the deep well region and a potential state of the second drain/source electrode, and the second discharge circuit provides a second discharge path between the second drain/source electrode and the power terminal according to the second control signal.

11. The electrostatic discharge protection circuit as claimed in claim 1 , further comprising:
a diode having an anode electrically connected to the power terminal and a cathode electrically connected to the second drain/source electrode,
wherein when the electrostatic discharge event occurs on the first drain/source electrode, a second discharge path is formed between the power terminal and the second drain/source electrode through the diode.

12. A semiconductor circuit comprising:
a semiconductor element formed in a well region and comprising a first drain/source electrode and a second drain/source electrode, wherein the well region is surrounded by a deep well region, the well has a first conductivity type, and the deep well region has a second conductivity type different from the first conductivity type;
a first control circuit electrically connected between the first drain/source electrode of the semiconductor element and a power terminal and comprising a first control terminal, wherein the first control terminal is electrically connected to the deep well region, and the first control circuit generates a first control signal; and
a first discharge circuit electrically connected between the first drain/source electrode and the power terminal and controlled by the first control signal,
wherein when an electrostatic discharge event occurs on the first drain/source electrode, the first control circuit generates the first control signal according to a potential state of the deep well region and a potential state of the first drain/source electrode, and the first discharge circuit provides a first discharge path between the first drain/source electrode and the power terminal according to the first control signal.

13. The semiconductor circuit as claimed in claim 12 , wherein the first control circuit comprises:
a first inverter electrically connected between the first drain/source electrode and the power terminal and comprising a first input terminal and a first output terminal,
wherein the first input terminal is electrically conne

Assignees

• Vanguard Int Semiconduct Corp

Inventors

• Wang yu-kai
• Lin Chang-Min
• Lee Jian-Hsing

Classifications

• H10D89/60

  Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] · CPC title

• H10D89/819 Primary

  Bias arrangements for gate electrodes of FETs, e.g. RC networks or voltage partitioning circuits (FETs in a Darlington configuration H10D89/817) · CPC title

• H02H9/046 Primary

  responsive to excess voltage appearing at terminals of integrated circuits · CPC title

• H01L27/0248

  Electricity · mapped topic