Semiconductor device

Patent metadata

Field	Value
Publication number	US-10790277-B2
Application number	US-201515553138-A
Country	US
Kind code	B2
Filing date	Jun 19, 2015
Priority date	Jun 19, 2015
Publication date	Sep 29, 2020
Grant date	Sep 29, 2020

Abstract

A semiconductor device provided with: a first input/output circuit connected to a first pad; a second input/output circuit disposed in the direction along one side constituted by a chip edge in relation to the first input/output circuit, the second input/output circuit being connected to a second pad; and an ESD protective circuit disposed near the outer-side chip edge of the first and second input/output circuits. The ESD protection circuit is provided with a resistor, a capacitor, an inverter, and an N-channel-type transistor.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a first input/output circuit connected to a first pad;
a second input/output circuit placed in a direction along one side constituted by a chip end with respect to the first input/output circuit and connected to a second pad; and
a first ESD (Electro-Static-Discharge) protection circuit placed in proximity to the chip end outside the first and second input/output circuits,
wherein the first ESD protection circuit includes a first resistor, a first capacitor, a first inverter, and a first N-channel transistor.

2. The semiconductor device according to claim 1 , comprising:
a first power supply wiring connected to a first power supply pad; and
a first grounding wire connected to a first ground pad.

3. The semiconductor device according to claim 2 ,
wherein the first and second input/output circuits respectively include a first diode having an anode connected to a signal wiring and a cathode connected to a first power supply wiring, a second diode having an anode connected to a first grounding wire and a cathode connected to the signal wiring, and an output circuit or an input circuit connected to the signal wiring.

4. The semiconductor device according to claim 3 ,
wherein one end of the first resistor is connected to the first power supply wiring,
wherein the other end of the first resistor is connected to one end of the first capacitor,
wherein the other end of the first capacitor is connected to the first grounding wire,
wherein the other end of the first resistor is connected to an input of a first inverter,
wherein an output of the first inverter is connected to the gate electrode of a first N-channel transistor, and
wherein the first N-channel transistor forms a current path between the first power supply wiring and the first grounding wire.

5. The semiconductor device according to claim 4 , comprising:
a third diode placed between the first input/output circuit and the second input/output circuit and having an anode connected to the first grounding wire and a cathode connected to the first power supply wiring.

6. The semiconductor device according to claim 2 , comprising:
a second ESD protection circuit placed in a direction along the side with respect to the first ESD protection circuit,
wherein the second ESD protection circuit includes a second resistor having one end connected to the first power supply wiring, a second capacitor having one end connected to the other end of the second resistor and the other end connected to the first grounding wire, a second inverter receiving input from the other end of the second resistor, and a second N-channel transistor having the gate electrode connected to an output of the second inverter and forming a current path between the first power supply wiring and the first grounding wire.

7. The semiconductor device according to claim 2 , comprising:
a third ESD protection circuit placed in the direction along the one side with respect to the first protection circuit,
wherein the third ESD protection circuit includes a third inverter receiving input from the other end of the first resistor and a third N-channel transistor having the gate electrode connected to an output of the third inverter and forming a current path between the first power supply wiring and the first grounding wire.

8. The semiconductor device according to claim 2 ,
wherein the first pad is superposed over a region where the first input/output circuit is formed as planarly viewed, and
wherein the second pad is superposed over a region where the second input/output circuit is formed as planarly viewed.

9. The semiconductor device according to claim 8 ,
wherein the first pad is superposed over a region where the first input/output circuit is formed and a region where the second input/output circuit is formed as planarly viewed, and
wherein the second pad is superposed over a region where the second input/output circuit is formed and a region where the first input/output circuit is formed as planarly viewed.

10. The semiconductor device according to claim 2 ,
wherein the first pad is placed between a region where the first ESD protection circuit is formed and the one side as planarly viewed, and
wherein the second pad is placed between a region where the first ESD protection circuit is formed and the one side as planarly viewed.

11. The semiconductor device according to claim 5 ,
wherein the first power supply wiring includes a third and a fourth power supply wirings extended in a direction along the one side,
wherein the first grounding wire includes a third and a fourth grounding wires extended in a direction along the one side,
wherein the third power supply wiring is connected to the cathode of the first diode and the cathode of the third diode,
wherein the third grounding wire is connected to the anode of the second diode and the anode of the third diode,
wherein the fourth power supply wiring is connected to one end of the first resistor and the first N-channel transistor, and
wherein the fourth grounding wire is connected to the other end of the first capacitor and the first N-channel transistor.

12. The semiconductor device according to claim 11 ,
wherein the fourth grounding wire, the fourth power supply wiring, the third grounding wire, and the third power supply wiring are placed in this order from the chip end side.

13. The semiconductor device according to claim 11 ,
wherein the fourth power supply wiring, the fourth grounding wire, the third grounding wire, and the third power supply wiring are placed in this order from the chip end side.

14. The semiconductor device according to claim 2 , comprising:
a second power supply wiring connected to a second power supply pad;
a second grounding wire connected to a second ground pad; and
a third ESD protection circuit placed in a direction along a chip edge side with respect to the first input/output circuit,
wherein the third ESD protection circuit includes a third resistor having one end connected to the second power supply wiring, a third capacitor having one end connected to the other end of the third resistor and the other end connected to the second grounding wire, a third inverter receiving input from the other end of the third resistor, a second N-channel transistor having the gate electrode connected to an output of the third inverter and forming a current path between the second power supply wiring and the second grounding wire, and a fourth diode having an anode connected to the second grounding wire and a cathode connected to the second power supply wiring.

15. The semiconductor device according to claim 14 , comprising:
a bridge circuit connecting the first grounding wire and the second grounding wire with each other,
wherein the bridge circuit includes a fifth diode having an anode connected to the first grounding wire and a cathode connected to the second grounding wire and a sixth diode having an anode connected to the second grounding wire and a cathode connected to the first grounding wire.

16. A semiconductor device comprising:
a first power supply domain connected to a first power supply pad and a first ground pad; and
a second power supply domain connected to a second power supply pad and a second ground pad,
wherein the first power supply domain includes:
a first input/output circuit connected to a first pad;
a second input/output circuit placed in a direction along one side constituted by a chip end with respect to the first input/output circuit and connected to a second pad; and

Assignees

• Renesas Electronics Corp

Inventors

• Maeda Satoshi
• Morishita Yasuyuki
• Tanaka Masanori

Classifications

• H10W72/00

  Interconnections or connectors in packages · CPC title

• H10W20/427

  Power or ground buses · CPC title

• H10D89/911

  using passive elements as protective elements · CPC title

• H10D89/811

  using FETs as protective elements · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title