Display apparatus having a transmitting area

Patent metadata

Field	Value
Publication number	US-11296180-B2
Application number	US-202117228636-A
Country	US
Kind code	B2
Filing date	Apr 12, 2021
Priority date	Jul 15, 2020
Publication date	Apr 5, 2022
Grant date	Apr 5, 2022

Abstract

A display apparatus includes a substrate including a transmitting area, a display area surrounding the transmitting area, a first non-display area disposed between the transmitting area and the display area, and a second non-display area surrounding the display area. A plurality of pixels is arranged in the display area. A set of 2n connection wirings (where n is a positive integer) is disposed in the first non-display area and each of the 2n connection wirings extends along at least a part of an edge of the transmitting area. Each of a plurality of voltage wirings extends in a first direction and is connected to at least some of pixels disposed in a common row from among the plurality of pixels. Each of the plurality of voltage wirings is connected to one of the 2n connection wirings.

First claim

What is claimed is:

1. A display apparatus, comprising:
a substrate comprising a transmitting area, a display area at least partially surrounding the transmitting area, a first non-display area disposed between the transmitting area and the display area, and a second non-display area at least partially surrounding the display area;
a plurality of pixels arranged within the display area;
a plurality of connection wirings disposed in the first non-display area, each of the plurality of connection wirings extending along at least a part of an edge of the transmitting area; and
a plurality of voltage wirings each of which extends in a first direction and connects to at least some of pixels disposed in a common row from among the plurality of pixels,
wherein the plurality of connection wirings includes 2n connection wirings, where n is a positive integer,
wherein each of the plurality of voltage wirings is connected to one of the 2n connection wirings, and
wherein first through 2n th voltage wirings from among the plurality of voltage wirings are connected in a one-to-one manner to the 2n connection wirings.

2. The display apparatus of claim 1 , wherein a connection wiring, from among the 2n connection wirings, connected to an i th voltage wiring from among the plurality of voltage wirings is the same as a connection wiring, from among the 2n connection wirings, connected to a (2n+i) th voltage wiring from among the plurality of voltage wirings, wherein i is a positive integer.

3. The display apparatus of claim 1 , further comprising:
a plurality of first scan lines each extending in the first direction and connected to the pixels disposed in the common row from among the plurality of pixels;
a plurality of second scan lines each extending in the first direction and connected to the pixels disposed in the common row from among the plurality of pixels; and
a gate driving circuit disposed in the second non-display area and configured to drive the plurality of first scan lines and the plurality of second scan lines,
wherein each of the plurality of first scan lines is additionally connected to pixels disposed in a previous row, that is previous to the common row, from among the plurality of pixels.

4. The display apparatus of claim 3 , wherein the gate driving circuit is configured to sequentially output first and second scan signals to the plurality of first and second scan lines in an MC n-clk mode,
wherein each of the plurality of first scan lines transmits n first scan signals during a first frame,
wherein each of the plurality of second scan lines transmits n second scan sigh is during a second frame, and
wherein the pixels alternately receive the n first scan signals and the as second scan signals.

5. The display apparatus of claim 4 , wherein, in a first interval, pixels connected to j th through (j+2n−1) th voltage wirings from among the plurality of voltage wirings receive an initialization voltage through the j th through (j+2n−1) th voltage wirings in response to the n first scan signals, wherein j is a positive integer.

6. The display apparatus of claim 5 , wherein the j th through (j+2n−1) th voltage wirings are connected to different connection wirings from among the 2n connection wirings.

7. The display apparatus of claim 2 , wherein pixels connected to a j th voltage wiring from among the plurality of voltage wirings receive an initialization voltage during k th through (k+2n−1) th intervals through the j th voltage wiring in response to the n first scan signals, wherein k is a positive integer.

8. The display apparatus of claim 1 , further comprising an initialization voltage supply wiring disposed in the second non-display area,
wherein a first end of the plurality of voltage wirings is connected to the 2n connection wirings, respectively, and a second end of the plurality of voltage wirings is connected to the initialization voltage supply wiring.

9. The display apparatus of claim 1 , wherein each of the plurality of voltage wirings comprises a plurality of first voltage wirings and a plurality of second voltage wirings spaced apart from each other by the transmitting area.

10. The display apparatus of claim 9 , wherein the 2n connection wirings comprise 2n first connection wirings and 2n second connection wirings disposed on opposite sides of the transmitting area, the 2n first connection wirings being spaced apart from the 2n second connection wirings.

11. The display apparatus of claim 10 , wherein each of the plurality of first voltage wirings is connected to one of the 2n first connection wirings, and
wherein each of the plurality of second voltage wirings is connected to one of the 2n second connection wirings.

12. The display apparatus of claim 1 , further comprising:
a storage capacitor comprising a lower electrode and an upper electrode disposed on and at least partially overlapping the lower electrode;
an insulating layer disposed on the storage capacitor; and
a data line disposed on the insulating layer,
wherein the plurality of voltage wirings and the upper electrode are disposed on the same layer, and
wherein the 2n connection wirings and the data line are disposed on the same layer.

13. The display apparatus of claim 1 , wherein each of the plurality of pixels receives first through third scan signals, a data voltage, and an initialization voltage, and comprises:
a light-emitting device;
a driving thin-film transistor configured to control a level of current flowing through the light-emitting device according to a gate-source voltage;
a storage capacitor disposed between a power supply line and a gate of the driving thin-film transistor;
a scan thin-film transistor configured to transmit the data voltage to a source of the driving thin-film transistor in response to the second scan signal;
a compensation thin-film transistor configured to connect a drain of the driving thin-film transistor to the gate of the driving thin-film transistor in response to the second scan signal;
a gate initialization thin-film transistor configured to apply the initialization voltage to the gate of the driving thin-film transistor in response to the first scan signal; and
an anode initialization thin-film transistor configured to apply the initialization voltage to an anode of the light-emitting device in response to the third scan signal.

14. The display apparatus of claim 13 , wherein for the pixels disposed in the common row from among the plurality of pixels, the first scan signal is synchronized with a second scan signal of a previous row, and the third scan signal is the same as a first scan signal of a next row.

15. A display apparatus, comprising:
a substrate comprising a transmitting area, a display area at least partially surrounding the transmitting area, a first non-display area disposed between the transmitting area and the display area, and a second non-display area at least partially surrounding the display area;
a plurality of pixels arranged in the display area;
six connection wirings disposed in the first non-display area and extending along at least a part of an edge of the transmitting area, and
a plurality of voltage wirings each extending in a first direction and connected to at least some of pixels disposed in a common row from among the plurality of pixels,
wherein each of the plurality of voltage wirings is connected to one of the six connection wirings, and
wherein first through sixth voltage wirings from among the plurality of voltage wirings are connected in a one-to-one manner to the six connection wirings.

Assignees

• Samsung Display Co Ltd

Inventors

• Kim Kyeonghwa
• Um Nuree
• Kim Kyunghoon
• Kim Mihae
• Noh Jaedu
• Oh Kyonghwan
• Lee Seunghee

Classifications

• G09G2320/0238

  Improving the black level · CPC title

• G09G2300/0861

  with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

• G09G2300/0819

  used for counteracting undesired variations, e.g. feedback or autozeroing · CPC title

• G09G2300/0439

  Pixel structures · CPC title