Display panel and electronic device including the same

US11114523B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11114523-B2
Application numberUS-201916687917-A
CountryUS
Kind codeB2
Filing dateNov 19, 2019
Priority dateNov 30, 2018
Publication dateSep 7, 2021
Grant dateSep 7, 2021

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A display panel includes a first panel region (FPR) including (n−1)-th and n-th pixel rows ((n−1)PR and nPR), and a second panel region (SPR) dividing the nPR to propagate an optical signal. The display panel includes a circuit element layer (CEL) and a display element layer (DEL). The CEL includes a signal line (SL), a pixel driving circuit (PDC), and first to third regions. The SL and the PDC are in the first region. The second region (SR) corresponds to the SPR. The SL and the PDC are not in the SR. The third region (TR) corresponds to the SPR and is along a periphery of the SR. The SL is in the TR, and includes an (n−1)-th scan line ((n−1)SL) connected to the (n−1)PR, an n-th reset line (nRL) connected to the nPR, and a first row connection line in the TR and connecting the (n−1)SL and the nRL.

First claim

Opening claim text (preview).

What is claimed is: 1. An electronic device comprising: a display panel comprising: a first panel region comprising: a first pixel; a second pixel disposed in a same pixel row as the first pixel; a third pixel disposed in a pixel row different from the pixel row of the first pixel and the second pixel; and a fourth pixel disposed in a same pixel row as the third pixel; and a second panel region having greater light transmittance than the first panel region; and a third panel region having greater light transmittance than the first panel region, wherein the first pixel, the second pixel, the third pixel, and the fourth pixel are disposed outside the second panel region, and the third panel region, the first pixel opposite to the second pixel with respect to the second panel region and the third panel region, and the third pixel is opposite to the fourth pixel with respect to the second panel region and the third panel region; and an optical film disposed on the display panel, wherein the display panel comprises: a circuit element layer comprising a signal line; pixel driving circuits configured to drive a corresponding pixel of the first pixel, the second pixel, the third pixel, and the fourth pixel; and a display element layer disposed on the circuit element layer, the display element layer comprising a display element and a dummy display element, wherein the circuit element layer comprises: a first region in which the signal line and the pixel driving circuits are disposed; a second region corresponding to the second panel region and the third panel region, the signal line and the pixel driving circuits being disposed outside the second region; a third region disposed along a periphery of the second region, the signal line being disposed in the third region; and a dummy region disposed between the second panel region and the third panel region, wherein the signal line comprises: a first scan line connected to the first pixel; a second scan line connected to the second pixel; a first reset line connected to the third pixel; a second reset line connected to the fourth pixel; and a connection line disposed in the third region and the dummy region, the connection line being electrically connected to the first scan line, the second scan line, the first reset line, and the second reset line; wherein the dummy display element is disposed in the dummy region, and laminated structures of the display element and the dummy display element are different from each other. 2. The electronic device of claim 1 , wherein: the pixel driving circuits comprise transistors; the transistors comprise: a first transistor; and a second transistor different from the first transistor; and the connection line is configured to provide a signal to the first transistors of each of the first pixel and the second pixel, and to the second transistor of each of the third pixel and the fourth pixel. 3. The electronic device of claim 2 , wherein the first and second scan lines and the first and second reset lines are disposed in a same layer as control electrodes of the first transistor. 4. The electronic device of claim 2 , wherein the connection line is disposed in a same layer as a capacitor electrode electrically connected to a corresponding first transistor. 5. The electronic device of claim 1 , wherein the optical film comprises an opening corresponding to the second panel region. 6. The electronic device of claim 1 , further comprising an electro-optical module configured to transmit or receive an optical signal, wherein the electro-optical module overlaps the second panel region. 7. The electronic device of claim 1 , wherein each of the second panel region and the third panel region comprises an opening penetrating from a bottom surface of the display panel to a top surface of the display panel. 8. The electronic device of claim 1 , wherein the pixel driving circuit is not disposed in the second panel region. 9. The electronic device of claim 1 , wherein: the circuit element layer further comprises a dummy pixel driving circuit disposed in the dummy region; and the pixel driving circuit and the dummy pixel driving circuit comprise a plurality of transistors having a same configuration. 10. The electronic device of claim 9 , wherein: the dummy display element is not electrically connected to the dummy pixel driving circuit, and the display element is electrically connected to the pixel driving circuit. 11. The electronic device of claim 1 , wherein: the first scan line, the second scan line, the first reset line, and the second reset line are disposed in a same layer; and the connection line and the first scan line are disposed in layers different from each other. 12. The electronic device of claim 1 , wherein the connection line comprise a first portion disposed in the third region and a second portion disposed in the dummy region. 13. The electronic device of claim 12 , wherein the first portion and the second portion are disposed in layers different from each other.

Assignees

Inventors

Classifications

  • Arrangements for improving contrast, e.g. preventing reflection of ambient light · CPC title

  • Self-supporting sealing arrangements · CPC title

  • Arrangements for improving contrast, e.g. preventing reflection of ambient light · CPC title

  • Self-supporting sealing arrangements · CPC title

  • OLEDs integrated with inorganic image sensors · CPC title

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Frequently asked questions

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What does patent US11114523B2 cover?
A display panel includes a first panel region (FPR) including (n−1)-th and n-th pixel rows ((n−1)PR and nPR), and a second panel region (SPR) dividing the nPR to propagate an optical signal. The display panel includes a circuit element layer (CEL) and a display element layer (DEL). The CEL includes a signal line (SL), a pixel driving circuit (PDC), and first to third regions. The SL and the PDC…
Who is the assignee on this patent?
Samsung Display Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10K59/131. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Sep 07 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 5 related publications on this page (citations in our corpus or others sharing the same primary CPC).