Fabrication methods

Patent metadata

Field	Value
Publication number	US-11296145-B2
Application number	US-201816484088-A
Country	US
Kind code	B2
Filing date	Oct 26, 2018
Priority date	Nov 15, 2017
Publication date	Apr 5, 2022
Grant date	Apr 5, 2022

Abstract

Various fabrication method are disclosed. In one such method, at least one structure is formed on a substrate which protrudes outwardly from a plane of the substrate. A beam is used to form a layer of material, at least part of which is in direct contact with a semiconductor structure on the substrate, the semiconductor structure comprising at least one nanowire. The beam has a non-zero angle of incidence relative to the normal of the plane of the substrate such that the beam is incident on one side of the protruding structure, thereby preventing a portion of the nanowire in a shadow region adjacent the other side of the protruding structure in the plane of the substrate from being covered with the material.

First claim

The invention claimed is:

1. A fabrication method comprising:
forming at least one structure on a substrate which protrudes outwardly from a plane of the substrate; and
using a beam to form a layer of material, at least part of which is in direct contact with a semiconductor structure on the substrate, the semiconductor structure comprising at least one nanowire, wherein the beam has a non-zero angle of incidence relative to the normal of the plane of the substrate such that the beam is incident on one side of the protruding structure, thereby preventing a portion of the nanowire in a shadow region adjacent the other side of the protruding structure in the plane of the substrate from being covered with the material.

2. The method of claim 1 , wherein the protruding structure is adjacent the nanowire, the shadow region extending across the width of the nanowire such that a section of the nanowire is not covered by a superconductor material across its entire width, thereby forming a junction between two further sections of the nanowire, both of which are at least partially covered by the superconductor material.

3. The method of claim 1 , wherein the protruding structure is a structure.

4. The method of claim 1 , wherein the protruding dielectric structure is formed of inorganic dielectric.

5. The method of claim 1 , wherein the at least one protruding structure is formed by depositing material on the substrate and selectively etching away the material to form the at least one protruding structure.

6. The method of claim 5 , further comprising:
using lithography to form an etching pattern, and
using the etching pattern for the selectively etching away of the material to form the at least one protruding structure.

7. The method of claim 1 , comprising:
forming a further layer of material using a beam at a different angle relative to the substrate, wherein said protruding structure or another protruding structure on the substrate prevents deposition of the further layer in a different shadow region.

8. The method of claim 7 , wherein the beam used to form the layer of material and the beam used to form the further layer of material are incident on the substrate with different azimuthal angles about an axis normal to the plane of the substrate.

9. The method of claim 8 , wherein the beam used to form the layer of material and the beam used to form the further layer of material are incident on the substrate at substantially the same angle of incidence relative to the axis normal to the plane of the substrate.

10. The method of claim 1 , wherein, in a masking phase, a dielectric mask is formed on the substrate, such that the dielectric mask leaves one or more regions of the substrate exposed; wherein, in a selective area growth phase, -semiconductor material is selectively grown on the substrate in the one or more exposed regions to form the semiconductor structure on the substrate.

11. The method of claim 1 , wherein the at least one nanowire is prepared externally and transferred to the substrate.

12. The method of claim 1 , wherein the material is a superconductor material.

Assignees

• Microsoft Technology Licensing Llc

Inventors

• Van Hoogdalem Kevin
• Kouwenhoven Leonardus
• Aseev Pavel
• Krogstrup Jeppesen Peter

Classifications

• G06N10/00

  Quantum computing, i.e. information processing based on quantum-mechanical phenomena · CPC title

• H10D62/121

  oriented parallel to substrates · CPC title

• H10D62/119

  Nanowire, nanosheet or nanotube semiconductor bodies · CPC title

• C30B11/12

  Vaporous components, e.g. vapour-liquid-solid-growth · CPC title

• G06N99/00

  Subject matter not provided for in other groups of this subclass · CPC title