Semiconductor memory device and manufacturing method of semiconductor memory device

Patent metadata

Field	Value
Publication number	US-11296111-B2
Application number	US-202016800812-A
Country	US
Kind code	B2
Filing date	Feb 25, 2020
Priority date	Jul 26, 2019
Publication date	Apr 5, 2022
Grant date	Apr 5, 2022

Abstract

According to one embodiment, a semiconductor memory device includes a stacked body of first conductor layers and second conductor layers. A pillar including a semiconductor layer extends along through the stacked body in a first direction. A charge storage layer is between the conductor layers and the semiconductor layer. The semiconductor layer includes a first portion extending along the first direction from an uppermost first conductor layer to a lowermost second conductor layer and a second portion above the first portion in the first direction. The second portion has a diameter that decreases with increasing distance along the first direction from the first portion.

First claim

What is claimed is:

1. A semiconductor memory device, comprising:
a stacked body including a plurality of first conductor layers and a plurality of second conductor layers above the plurality of first conductor layers in a first direction;
a pillar including a semiconductor layer, the pillar extending along the first direction within the stacked body; and
a charge storage layer between the plurality of first conductor layers and the semiconductor layer and between the plurality of second conductor layers and the semiconductor layer, wherein
the semiconductor layer includes:
a first portion extending along the first direction from an uppermost first conductor layer among the plurality of first conductor layers to a lowermost second conductor layer among the plurality of second conductor layers;
a second portion above the first portion in the first direction;
a third portion above the second portion in the first direction, the third portion having a diameter that increases with increasing distance along the first direction from the second portion;
a fourth portion below the first portion in the first direction, the fourth portion having a diameter that decreases at a first rate with increasing distance from the first portion along the first direction; and
a fifth portion below the fourth portion in the first direction, the fifth portion having a diameter that decreases at a second rate with increasing distance from the first portion along the first direction, the second rate being lower than the first rate, and

the second portion has a diameter that decreases with increasing distance along the first direction from the first portion.

2. The semiconductor memory device according to claim 1 wherein a lower surface of the lowermost second conductor layer intersects a surface of a portion of the lowermost second conductor layer facing the third portion of the semiconductor layer.

3. The semiconductor memory device according to claim 1 , wherein
the charge storage layer includes:
a first charge storage layer portion extending along the first direction between the uppermost first conductor layer and the lowermost second conductor layer, and
a second charge storage layer portion above the first charge storage layer portion and having a diameter that increases with distance upward along the first direction, and

the first charge storage layer portion and the second charge storage layer portion are continuous films.

4. The semiconductor memory device according to claim 3 , wherein
the charge storage layer further includes:
a fifth charge storage layer portion connecting the first charge storage layer portion and the second charge storage layer portion, and

a film thickness of the fifth charge storage layer portion is less than a film thickness of the first charge storage layer portion and less than a film thickness of the second charge storage layer portion.

5. The semiconductor memory device according to claim 3 , wherein the charge storage layer further includes:
a third charge storage layer portion between the first and second charge storage layer portions, the third charge storage layer portion having a diameter that decreases with distance upward along the first direction between the first charge storage layer portion and the second charge storage layer portion.

6. The semiconductor memory device according to claim 5 , wherein the charge storage layer further includes:
a fourth charge storage layer portion extending in a second direction crossing the first direction, the fourth charge storage layer portion being between the first charge storage layer portion and the third charge storage layer portion.

7. The semiconductor memory device according to claim 1 , wherein the lowermost second conductor layer has a surface facing the second portion of the semiconductor layer.

8. The semiconductor memory device according to claim 1 , further comprising:
a first insulator layer between the charge storage layer and the semiconductor layer, wherein
the first insulator layer includes:
a first insulating portion extending along the first direction between the uppermost first conductor layer and the lowermost second conductor layer, and
a second insulating portion above the first insulating portion and having a diameter that increases with distance upwards in the first direction, and

the first insulating portion and the second insulating portion of the first insulator layer are separated.

9. The semiconductor memory device according to claim 8 , wherein
the charge storage layer includes:
a first charge storage layer portion extending along the first direction between the uppermost first conductor layer and the lowermost second conductor layer, and
a second charge storage layer portion above the first charge storage layer portion in the first direction and having a diameter that increases with distance upward along the first direction, and

the first charge storage layer portion and the second charge storage layer portion are separated.

10. The semiconductor memory device according to claim 9 , further comprising:
a second insulator layer between the plurality of first conductor layers and the charge storage layer and between the plurality of second conductor layers and the charge storage layer, wherein
the second insulator layer includes:
a first portion extending along the first direction between the uppermost first conductor layer and the lowermost second conductor layer, and
a second portion above the first portion of the second insulator layer in the first direction and having a diameter that increases with distance upward along the first direction, and

the first portion of the second insulator layer and the second portion of the second insulator layer are continuous films.

11. The semiconductor memory device according to claim 10 , wherein
the second insulator layer further includes:
a third portion connecting the first portion of the second insulator layer and the second portion of the second insulator layer, and

a film thickness of the third portion of the second insulator layer is less than a film thickness of the first portion of the second insulator layer and a film thickness of the second portion of the second insulator layer.

12. The semiconductor memory device according to claim 1 , further comprising:
a first insulator layer between the charge storage layer and the semiconductor layer, wherein
the first insulator layer includes:
a first portion extending along the first direction between the uppermost first conductor layer and the lowermost second conductor layer, and
a second portion above the first portion of the first insulator layer in the first direction and having a diameter that increases with distance upward along the first direction, and

the first portion of the first insulator layer and the second portion of the first insulator layer are continuous films.

13. The semiconductor memory device according to claim 12 , wherein
the first insulator layer further includes:
a third portion connecting the first portion of the first insulator layer and the second portion of the first insulator layer, and

a film thickness of the third portion of the first insulator layer is less than a film thickness of the first portion of the first insulator layer and less than a film thickness of the second portion of the first insulator layer.

14. The semiconductor memory device according to claim 1 , wherein a distance along the first direction between the uppermost first conductor layer and the lowermost second conductor layer is greater than a distance along the first direction be

Assignees

• Kioxia Corp

Inventors

• Mitsuno Yosuke
• Hamada Tatsufumi
• Sotome Shinichi
• Kuki Tomohiro
• Akeboshi Yuya

Classifications

• H10D64/037

  comprising charge-trapping insulators · CPC title

• H10D64/035

  comprising conductor-insulator-conductor-insulator-semiconductor structures · CPC title

• H01L27/11556

  Electricity · mapped topic

• H01L27/1157

  Electricity · mapped topic

• H01L29/40117

  Electricity · mapped topic