Through-substrate vias with improved connections

Patent metadata

Field	Value
Publication number	US-11296011-B2
Application number	US-201916459387-A
Country	US
Kind code	B2
Filing date	Jul 1, 2019
Priority date	Apr 28, 2010
Publication date	Apr 5, 2022
Grant date	Apr 5, 2022

Abstract

A device includes a substrate, and a plurality of dielectric layers over the substrate. A plurality of metallization layers is formed in the plurality of dielectric layers, wherein at least one of the plurality of metallization layers comprises a metal pad. A through-substrate via (TSV) extends from the top level of the plurality of the dielectric layers to a bottom surface of the substrate. A deep conductive via extends from the top level of the plurality of dielectric layers to land on the metal pad. A metal line is formed over the top level of the plurality of dielectric layers and interconnecting the TSV and the deep conductive via.

First claim

What is claimed is:

1. A device comprising:
a substrate;
an interconnect structure over the substrate, the interconnect structure comprising a stacked plurality of metal layers the plurality of metal layers including respective metal features embedded within respective ones of a plurality of low-k dielectric layers, the interconnect structure having a topmost metal layer surface; and
a passivation layer on and directly over the topmost metal layer surface, wherein a k value of the passivation layer is higher than k values of the plurality of low-k dielectric layers;

a through-substrate via (TSV) extending through the passivation layer and into the substrate;
a first conductive via on a first side of the TSV and laterally spaced apart from at least one metal feature of the interconnect structure and extending through the passivation layer and terminating on a first metal pad in a first metal layer of the stacked plurality of metal layers;
a second conductive via on the first side of the TSV and laterally spaced apart from at least one other metal feature of the interconnect structure and extending through the passivation layer, extending through the first layer of the stacked plurality of metal layers, and terminating on a second metal pad in a second metal layer of the stacked plurality of metal layers different from the first layer of the stacked plurality of metal layers; and
a conductor above the interconnect structure and electrically coupling the TSV to the first and the second conductive vias.

2. The device of claim 1 , wherein the TSV extends completely through the substrate.

3. The device of claim 1 , wherein the TSV and the first and the second conductive vias form a continuous conductor with no diffusion barrier layer separating the TSV from the first and the second conductive vias.

4. The device of claim 1 , wherein:
the first conductive via has a first width when viewed from cross section and a first height extending from topmost surface to bottommost surface of the first conductive via;
the second conductive via has a second width when viewed from cross section and a second height extending from topmost surface to bottommost surface of the second conductive via;
the TSV has a third width when viewed from cross section and a third height extending from topmost surface to bottommost surface of the TSV;
the third width is greater than the second width and the first width and the third height is greater than the second height and the first height; and
the second width is greater than the first width and the second height is greater than the first height.

5. The device of claim 1 , wherein the TSV comprises a metal selected from the group consisting of copper, copper alloys, aluminum, silver, and gold.

6. The device of claim 1 , further comprising a third deep conductive via extending from the top surface of the passivation layer to land on a third metal pad in a third one of the stacked plurality of metallization layers different from the first one and the second one.

7. The device of claim 1 , wherein:
the second conductive via lands on the first metal pad.

8. The device of claim 1 , further comprising a barrier layer encompassing the TSV.

9. The device of claim 8 , wherein the barrier layer comprises a material selected from the group consisting of titanium, titanium nitride, tantalum, tantalum nitride, and combinations thereof.

10. A device comprising:
a substrate;
an interconnect structure over the substrate, the interconnect structure comprising:
a plurality of metallization layers comprising:
a bottom metallization layer (M1) including a bottom conductive feature embedded in a bottom dielectric layer;
an intermediate metallization layer (M2) over the M1 layer the intermediate metallization layer including an intermediate conductive feature embedded in an intermediate dielectric layer;
a second metallization layer (M3) over the M2 the second metallization layer including an second conductive feature embedded in a second dielectric layer; and
a top metallization layer (Mtop) over the M2 the top metallization layer including an top conductive feature embedded in an top dielectric layer; and

a through-substrate via (TSV) extending from the Mtop to a bottom surface of the substrate;
a passivation layer, different than the top dielectric layer over the top dielectric layer;
a first conductive via laterally spaced apart from the TSV and extending from a top surface of the passivation layer and physically and electrically contacting the intermediate conductive feature of the M2;
a second conductive via laterally spaced apart from the TSV and extending from a top surface of the passivation layer and physically and electrically contacting the second conductive feature of the M3, the first conductive via and the second conductive via being on the same side of the TSV; and
a metal line electrically connecting the TSV and one of the first conductive via and the second conductive via.

11. The device of claim 10 , wherein the passivation layer is formed of a non-low-k dielectric material.

12. The device of claim 10 , wherein the TSV and the first and the second conductive vias form a continuous region with no diffusion barrier layer separating the TSV from the first and the second conductive vias.

13. The device of claim 10 , wherein:
the first conductive via has a first width when viewed from cross section and a first height extending from topmost surface to bottommost surface of the first conductive via;
the second conductive via has a second width when viewed from cross section and a second height extending from topmost surface to bottommost surface of the second conductive via;
the TSV has a third width when viewed from cross section and a third height extending from topmost surface to bottommost surface of the TSV;
the third width is greater than the second width and the first width and the third height is greater than the second height and the first height; and
the second width is greater than the first width and the second height is greater than the first height.

14. The device of claim 10 , further comprising:
a metal bump over the passivation layer, the metal bump disposed outside a lateral extent of the metal line.

15. The device of claim 10 , further comprising:
an interlayer dielectric (ILD) disposed over the substrate and under the plurality of metallization layers.

16. The device of claim 11 , further comprising a third deep conductive via extending from the top surface of the dielectric layer to land on a metal pad in a third one of the plurality of metallization layers different from the first one and the second one.

17. The device of claim 16 , wherein the metal pad is positioned in a bottommost level of the plurality of metallization layers.

18. A device comprising:
a plurality of dielectric layers;
a plurality of metallization layers formed respectively in the plurality of dielectric layers;
a first conductive via extending from the top level of the plurality of dielectric layers through at least two layers of the plurality of dielectric layers and physically and electrically connecting with a first metallization layer of the plurality of metallization layers;
a second conductive via extending from the top level of the plurality of dielectric layers through at least three layers of the plurality of dielectric layers and physically and electrically connecting with a second metallization layer of the plurality of metallization layers, the second metallization layer being above the first met

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Jing-Cheng
• Yang Ku-Feng

Classifications

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/248

  Top-view layouts, e.g. mirror arrays · CPC title

• H10W72/244

  relative to underlying supporting features, e.g. bond pads, RDLs or vias · CPC title