Stiffener and package substrate for a semiconductor package

Patent metadata

Field	Value
Publication number	US-11295998-B2
Application number	US-201815945641-A
Country	US
Kind code	B2
Filing date	Apr 4, 2018
Priority date	Apr 4, 2018
Publication date	Apr 5, 2022
Grant date	Apr 5, 2022

Abstract

Techniques for fabricating a package substrate and/or a stiffener for a semiconductor package are described. For one technique, a package substrate comprises: a routing layer comprising a dielectric layer. A stiffener may be above the routing layer and a conductive line may be on the routing layer, the conductive line comprising first and second portions, the first portion having a first width, the second portion having a second width, the conductive line extending from a first region of the routing layer to a second region of the routing layer, the first region being under the stiffener, the second region being outside the stiffener, the first portion being on the first region, and the second portion being on the second region. One or more portions of the conductive line can be perpendicular to an edge of the stiffener. The perpendicular portion(s) may comprise a transition between the first and second widths.

First claim

What is claimed is:

1. A package substrate, comprising:
a routing layer, the routing layer comprising a dielectric layer;
a stiffener above the routing layer, the stiffener comprising an opening; and
a conductive line on the routing layer, the conductive line comprising a first portion and a second portion continuous along a length, the first portion having a first width, the second portion having a second width different than the first width, the conductive line extending from a first region of the routing layer to a second region of the routing layer, the first region being under the stiffener, the second region being outside the stiffener, the first portion being on the first region, and the second portion being on the second region.

2. The package substrate of claim 1 , wherein the first width is less than the second width.

3. The package substrate of claim 1 , wherein at least one portion of the conductive line is perpendicular to an edge of the stiffener on the conductive line.

4. The package substrate of claim 3 , wherein the at least one portion of the conductive line that is perpendicular to the edge of the stiffener comprises a transition from the first width to the second width.

5. The package substrate of claim 1 , wherein the stiffener includes an exclusion zone and wherein no conductive line on the routing layer is under the exclusion zone.

6. The package substrate of claim 1 , further comprising another conductive line adjacently located on the routing layer next to the conductive line, wherein a pitch between the two adjacent conductive lines is a function of a difference between the first width and the second width.

7. The package substrate of claim 1 , further comprising another conductive line adjacently located on the routing layer next to the conductive line, wherein a pitch between the two adjacent conductive lines is a selected from a range of values comprising 18-80 micrometers (μm).

8. The package substrate of claim 1 , wherein the first width is less than or equal to 18 μm and the second width is greater than or equal to 34 μm.

9. The package substrate of claim 1 , wherein a ratio of the first width to the second width is 9:17.

10. The package substrate of claim 1 , wherein the conductive line transitions from the first width to the second width within a tolerance region and wherein an edge of the stiffener is within the tolerance region.

11. The package substrate of claim 1 , wherein a length of the stiffener is less than, approximately equal to, or equal to 8000 μm.

12. The package substrate of claim 11 , wherein an electrical ground is positioned on the routing layer at half the length of the stiffener.

13. The package substrate of claim 1 , wherein a clearing area on the routing layer between an electrical ground and an edge of the stiffener is less than, approximately equal to, or equal to 310 μm.

14. The package substrate of claim 1 , wherein an impedance of the conductive line is less than, approximately equal to, or equal to 40 ohms (Ω).

15. A method of fabricating a package substrate, comprising:
forming a routing layer, the routing layer comprising a dielectric layer;
placing a stiffener above the routing layer, the stiffener comprising an opening; and
forming a conductive line on the routing layer, the conductive line comprising a first portion and a second portion continuous along a length, the first portion having a first width, the second portion having a second width different than the first width, the conductive line extending from a first region of the routing layer to a second region of the routing layer, the first region being under the stiffener, the second region being outside the stiffener, the first portion being on the first region, and the second portion being on the second region.

16. The method of claim 15 , wherein the first width is less than the second width.

17. The method of claim 15 , wherein forming a conductive line on the routing layer comprises forming at least one portion of the conductive line to be perpendicular to an edge of the stiffener on the conductive line.

18. The method of claim 17 , wherein forming at least one portion of the conductive line to be perpendicular to an edge of the stiffener on the conductive line comprises forming the at least one portion of the conductive line that is perpendicular to the edge of the stiffener to comprise a transition from the first width to the second width.

19. The method of claim 18 , wherein the conductive line transitions from the first width to the second width within a tolerance region and wherein an edge of the stiffener is within the tolerance region.

20. The method of claim 15 , wherein the stiffener includes an exclusion zone and wherein no conductive line on the routing layer is under the exclusion zone.

21. A package substrate, comprising:
a routing layer, the routing layer comprising a dielectric layer;
a stiffener above the routing layer, the stiffener comprising an opening;
a semiconductor die on the routing layer, wherein the semiconductor die fits into the opening of the stiffener;
a first conductive line on the routing layer, the first conductive line comprising a first portion and a second portion continuous along a length, the first portion having a first width, the second portion having a second width different than the first width, the first conductive line extending from a first region of the routing layer to a second region of the routing layer, the first region being under the stiffener, the second region being outside the stiffener, the first portion being on the first region, and the second portion being on the second region; and
a second conductive line on the routing layer.

22. The package substrate of claim 21 , wherein the first width is less than the second width.

23. The package substrate of claim 22 , wherein the second conductive line has a third width that is less than or equal to the second width.

24. The package substrate of claim 21 , wherein at least one portion of the first conductive line is perpendicular to an edge of the stiffener on the first conductive line.

25. The package substrate of claim 24 , wherein the at least one portion of the conductive line that is perpendicular to the edge of the stiffener comprises a transition from the first width to the second width.

26. A package substrate, comprising:
a routing layer, the routing layer comprising a dielectric layer;
a stiffener above the routing layer, the stiffener comprising an opening;

a conductive line on the routing layer, the conductive line comprising a first portion and a second portion, the first portion having a first width, the second portion having a second width, the conductive line extending from a first region of the routing layer to a second region of the routing layer, the first region being under the stiffener, the second region being outside the stiffener, the first portion being on the first region, and the second portion being on the second region; and
another conductive line adjacently located on the routing layer next to the conductive line, wherein a pitch between the two adjacent conductive lines is a function of a difference between the first width and the second width.

27. A package substrate, comprising:
a routing layer, the routing layer comprising a dielectric layer;
a stiffener above the routing layer, the stiffener comprising

Assignees

• Intel Corp

Inventors

• Christianson Stephen
• Hall Stephen
• Davies-Venn Emile
• Han Dong-Ho
• Aygun Kemal
• Ganguly Konika
• Liao Jun
• Zamani M Reza
• Mason Cory
• Kamisetty Kirankumar

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W44/216

  Waveguides, e.g. strip lines · CPC title

• H10W70/05

  of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) · CPC title

• H10W44/20

  at high-frequency [HF] or radio frequency [RF] · CPC title

• H10W42/121

  protecting against mechanical damage (H10W76/00, H10W74/00 take precedence) · CPC title