Multiplexed two-step neural ADC

Patent metadata

Field	Value
Publication number	US-11290125-B2
Application number	US-202017128095-A
Country	US
Kind code	B2
Filing date	Dec 19, 2020
Priority date	Dec 20, 2019
Publication date	Mar 29, 2022
Grant date	Mar 29, 2022

Abstract

An analog-to-digital converter, ADC, module is configured to operate in a coarse conversion ADC phase, and a fine conversion ADC phase comprising a delta modulation loop for tracking a signal, wherein the ADC module is configured to, at initiation of input of an analog signal, operate in the coarse conversion ADC phase for determining a coarse digital value; wherein the ADC module is configured to, when the coarse digital value is determined, operate in the fine conversion ADC phase, receive the coarse digital value as an initial approximation of the analog signal and track the analog signal during a finite duration.

First claim

The invention claimed is:

1. An analog-to-digital converter, ADC, module,
wherein the ADC module is configured to operate in a coarse conversion ADC phase, and a fine conversion ADC phase comprising a delta modulation loop for tracking a signal,
wherein the ADC module is configured to, at initiation of input of an analog signal, operate in the coarse conversion ADC phase for determining a coarse digital value of the analog signal;
wherein the ADC module is configured to, when the coarse digital value is determined, operate in the fine conversion ADC phase, wherein the ADC module operating in the fine conversion ADC phase is configured to receive the coarse digital value as an initial approximation of the analog signal in an integrator of the delta modulation loop and is configured to track the analog signal during a finite duration.

2. The ADC module according to claim 1 , wherein the ADC module in the fine conversion ADC phase provides an incremental ADC.

3. The ADC module according to claim 2 , wherein the ADC module in the fine conversion ADC phase provides a delta-delta-sigma modulator ADC comprising an inner delta-sigma modulator with an outer delta modulator.

4. The ADC module according to claim 3 , wherein the outer delta modulator comprises a digital integrator followed by a digital-to-analog converter.

5. The ADC module according to claim 1 , wherein the ADC module is configured to operate in the coarse conversion ADC phase using successive approximation.

6. The ADC module according to claim 1 , wherein the ADC module is connected to a decimation filter for providing output from the ADC module operating in the fine conversion ADC phase to the decimation filter for down-sampling of output from the fine conversion ADC phase.

7. The ADC module according to claim 1 , wherein the ADC module is configured to be controlled to selectively activate the coarse conversion ADC phase or the fine conversion ADC phase.

8. The ADC module according to claim 7 , wherein the ADC module is configured to re-use at least one component, such as a multi-bit DAC and/or a single-bit comparator, when operating in the coarse conversion ADC phase and the fine conversion ADC phase.

9. An ADC circuitry, comprising:
a multiplexer input configured to receive a plurality of analog signals and configured to output a time division multiplexed sequence of the plurality of analog signals, wherein each of the plurality of analog signals forms at least one sub-sequence within the sequence, and the ADC module according to claim 1 ;
wherein the ADC module is configured to, at initiation of a sub-sequence of an analog signal within the sequence of the plurality of analog signals, operate in the coarse conversion ADC phase, and
wherein the ADC module operating in the fine conversion ADC phase is configured to track the analog signal during the sub-sequence.

10. The ADC circuitry according to claim 9 , wherein each of the plurality of analog signals forms at least a first sub-sequence and a second sub-sequence within the sequence, wherein the ADC circuitry further comprises a memory for storing an end value determined by tracking the analog signal during the first sub-sequence, and wherein the ADC module is configured to, at initiation of the second sub-sequence of the analog signal, operate in the coarse conversion ADC phase receiving output from the multiplexer for determining a coarse digital value of the analog signal and receiving the end value from the memory as an initial approximation for determining the coarse digital value.

11. A sensor unit comprising:
a set of sensors configured to record electrical signals; and
the ADC circuitry according to claim 9 , wherein the ADC circuitry is connected to at least a subset of the set of sensors for receiving the plurality of analog signals.

12. A neural probe comprising:
a carrier adapted for being inserted into neural tissue of a brain;
the sensor unit according to claim 11 , wherein the set of sensors is arranged on the carrier for recording electrical signals from sensing in the brain.

13. The neural probe according to claim 12 , wherein the ADC circuitry is arranged on the carrier.

14. A micro-electrode array, comprising:
a carrier providing a surface for receiving a sample of biological matter; and
the sensor unit according to claim 11 , wherein the set of sensors is arranged on the carrier for recording electrical signals in the sample of biological matter.

15. The micro-electrode array according to claim 14 , wherein the ADC circuitry is arranged on the carrier.

16. A method for analog-to-digital conversion, said method comprising:
receiving an analog signal;
at initiation of the analog signal, performing a coarse analog-to-digital conversion for determining a coarse digital value of the analog signal;
performing a fine analog-to-digital conversion using the coarse digital value as an initial approximation of the analog signal, wherein the fine analog-to-digital conversion uses a delta modulation loop for tracking the analog signal during a finite duration.

Assignees

• Imec Vzw

Inventors

• Ballini Marco

Classifications

• H03M3/474

  using time-division multiplexing · CPC title

• H03M1/1225

  using time-division multiplexing · CPC title

• A61N1/025

  Digital circuitry features of electrotherapy devices, e.g. memory, clocks, processors · CPC title

• H03M3/462 Primary

  Details relating to the decimation process (decimation filters in general H03H17/0416, H03H17/0621) · CPC title

• H03M3/422

  having one quantiser only · CPC title