Compensation circuit for delta-sigma modulators, corresponding device and method

Patent metadata

Field	Value
Publication number	US-11290124-B2
Application number	US-202117163230-A
Country	US
Kind code	B2
Filing date	Jan 29, 2021
Priority date	Jan 31, 2020
Publication date	Mar 29, 2022
Grant date	Mar 29, 2022

Abstract

A delta-sigma modulation circuit has a sampling period and, in operation, generates a delta-sigma modulated signal based on the analog input signal. The delta-sigma modulation circuit includes: a first integrator; an analog-to-digital converter; a feedback-loop coupled between an input of the first integrator and the output interface; a second integrator coupled between the first integrator and the analog-to-digital converter. The delta-sigma modulation circuit has loop-delay compensation circuitry having a plurality of switches. The loop delay compensation circuitry, in operation, controls the plurality of switches based on a time interval of a duration of half the sampling period and generates a loop-delay compensation signal.

First claim

The invention claimed is:

1. A system, comprising:
an input interface, which, in operation, receives an analog input signal;
an output interface, which, in operation, outputs a delta-sigma modulated signal; and
a delta-sigma modulation circuit having a sampling period and coupled between the input interface and the output interface, wherein the delta-sigma modulation circuit, in operation, generates the delta-sigma modulated signal based on the analog input signal, the delta-sigma modulation circuit including:
a first integrator;
an analog-to-digital converter coupled to the output interface;
a feedback-loop coupled between an input of the first integrator and the output interface;
a second integrator coupled between the first integrator and the analog-to-digital converter; and
loop-delay compensation circuitry having a plurality of switches, wherein the loop delay compensation circuitry, in operation, controls the plurality of switches based on a time interval of a duration of half the sampling period and generates a loop-delay compensation signal, wherein

the loop-delay compensation circuitry includes a derivative circuit coupled between an output of the first integrator and the plurality of switches;
the feedback-loop includes:
a first adder having a first input coupled to the input interface and an output coupled to an input of the first integrator; and
a first digital-to-analog converter coupled between the output interface and a second input of the first adder; and

the delta-sigma modulation circuit includes:
a second adder having a first input coupled to an output of the first integrator, a second input coupled to an output of the loop-delay compensation circuitry, and an output coupled to the second integrator; and
a third adder having a first input coupled to an output of the first integrator, a second input coupled to an output of the second integrator and an output coupled to the analog-to-digital converter.

2. The system of claim 1 wherein,
the first digital-to-analog converter, in operation, generates a first weighted feedback signal.

3. The system of claim 1 wherein the delta-sigma modulation circuit comprises an inverter coupled between the output of the first integrator and the first input of the third adder.

4. A system, comprising:
an input interface, which, in operation, receives an analog input signal;
an output interface, which, in operation, outputs a delta-sigma modulated signal; and
a delta-sigma modulation circuit having a sampling period and coupled between the input interface and the output interface, wherein the delta-sigma modulation circuit, in operation, generates the delta-sigma modulated signal based on the analog input signal, the delta-sigma modulation circuit including:
a first integrator;
an analog-to-digital converter coupled to the output interface;
a feedback-loop coupled between an input of the first integrator and the output interface;
a second integrator coupled between the first integrator and the analog-to-digital converter; and
loop-delay compensation circuitry having a plurality of switches, wherein the loop delay compensation circuitry, in operation, controls the plurality of switches based on a time interval of a duration of half the sampling period and generates a loop-delay compensation signal, wherein

the loop-delay compensation circuitry includes a derivative circuit coupled between an output of the first integrator and the plurality of switches; and
the loop-delay compensation circuitry comprises a third integrator coupled to an output of the plurality of switches.

5. The system of claim 4 wherein,
the feedback-loop includes:
a first adder having a first input coupled to the input interface and an output coupled to an input of the first integrator;
a first digital-to-analog converter coupled between the output interface and a second input of the first adder;
a second adder having a first input coupled to an output of the first integrator and an output coupled to an input of the second integrator; and
a second digital-to-analog converter coupled between the output interface and a second input of the second adder; and

the loop-delay compensation circuitry comprises a third adder having a first input coupled to an output of the second integrator, a second input coupled to an output of the third integrator and an output coupled to the analog-to-digital converter.

6. The system of claim 5 wherein,
the first digital-to-analog converter, in operation, generates a first weighted feedback signal; and
the second digital-to-analog converter, in operation, generates a second weighted feedback signal.

7. The system of claim 4 wherein,
the feedback-loop includes:
a first adder having a first input coupled to the input interface and an output coupled to an input of the first integrator; and
a first digital-to-analog converter coupled between the output interface and a second input of the first adder; and

the loop-delay compensation circuitry comprises a second adder having a first input coupled to an output of the second integrator, a second input coupled to an output of the third integrator and an output coupled to the analog-to-digital converter.

8. The system of claim 7 wherein,
the first digital-to-analog converter, in operation, generates a first weighted feedback signal.

9. The system of claim 7 wherein,
the delta-sigma modulation circuit includes a third adder coupled between the output of the second integrator and the second adder, the third adder having a first input coupled to an output of the first integrator, a second input coupled to the output of the second integrator and an output coupled to the first input of the second adder.

10. The system of claim 9 wherein the delta-sigma modulation circuit comprises an inverter coupled between the output of the first integrator and the first input of the third adder.

11. The system of claim 4 wherein,
the feedback-loop includes:
a first adder having a first input coupled to the input interface and an output coupled to an input of the first integrator;
a first digital-to-analog converter coupled between the output interface and a second input of the first adder;
a second adder having a first input coupled to an output of the first integrator and an output coupled to an input of the second integrator; and
a second digital-to-analog converter coupled between the output interface and a second input of the second adder; and

an output of the loop-delay compensation circuitry is coupled to a third input of the second adder.

12. The system of claim 11 wherein,
the first digital-to-analog converter, in operation, generates a first weighted feedback signal; and
the second digital-to-analog converter, in operation, generates a second weighted feedback signal.

13. A system, comprising:
an input interface, which, in operation, receives an analog input signal;
an output interface, which, in operation, outputs a delta-sigma modulated signal; and
a delta-sigma modulation circuit having a sampling period and coupled between the input interface and the output interface, wherein the delta-sigma modulation circuit, in operation, generates the delta-sigma modulated signal based on the analog input signal, the delta-sigma modulation circuit including:
a first integrator;
an analog-to-digital converter coupled to the output interface;
a feedback-loop coupled between an input of the first integrator and the output interface;
a second integrator coupled between the first integrator and the analog-to-digital converter; and
loop-delay compensation circuitry having a plurality of switches,

Assignees

• St Microelectronics Srl

Inventors

• Modaffari Roberto
• Pesenti Paolo
• Nicollini Germano

Classifications

• H03M3/02 Primary

  Delta modulation, i.e. one-bit differential modulation {(H03M3/30 takes precedence)} · CPC title

• H03M3/452

  with weighted feedforward summation, i.e. with feedforward paths from more than one filter stage to the quantiser input · CPC title

• H03M3/37 Primary

  Compensation or reduction of delay or phase error · CPC title

• H03M3/464

  Details of the digital/analogue conversion in the feedback path · CPC title