Method and system for an asynchronous successive approximation register analog-to-digital converter with word completion algorithm

Patent metadata

Field	Value
Publication number	US-11290122-B2
Application number	US-202016983888-A
Country	US
Kind code	B2
Filing date	Aug 3, 2020
Priority date	Jun 29, 2018
Publication date	Mar 29, 2022
Grant date	Mar 29, 2022

Abstract

Systems and methods for an asynchronous successive approximation register analog-to-digital converter (SAR ADC) with word completion algorithm may include a SAR ADC comprising a plurality of switched capacitors, a comparator, a metastability detector including a timer having a tunable time interval, and a successive approximation register. The SAR ADC may sample input signals at inputs of the switched capacitors; compare signals at outputs of the switched capacitors, each for a respective bit; sense whether a metastability condition exists for the comparator using the timer and setting a metastability flag upon each metastability detection for each bit; increase a value of the tunable time interval if more than one metastability flag is set during conversion of a sampled input signal; decrease a value of the tunable time interval if no metastability flags are set; and use the flags for a word completion in the cases when not all the bits have been evaluated.

First claim

What is claimed is:

1. A method of operating a successive approximation register (SAR) analog-to-digital converter (ADC), the method comprising:
comparing output signals at outputs of a plurality of switched capacitors;
determining, based on a value of a tunable time interval, whether to set a respective metastability flag for each bit of a plurality of bits to be evaluated; and
updating the value of the tunable time interval based on a count of the metastability flags that have been set.

2. The method of claim 1 , further comprising:
using the metastability flags for word completion when not all of the plurality of bits have been evaluated; and
determining an output value based on a final value of the SAR and word completion.

3. The method of claim 2 , wherein using the metastability flags for word completion comprises:
for each non-evaluated bit of the plurality of bits, assigning a value complementary to the respective non-evaluated bit.

4. The method of claim 1 , wherein the count is greater than one, wherein updating the value of the tunable time interval comprises:
increasing the value of the tunable time interval.

5. The method of claim 1 , wherein the count is zero, wherein updating the value of the tunable time interval comprises:
decreasing the value of the tunable time interval.

6. The method of claim 1 , wherein the metastability flags are stored in a metastability flag register of the SAR ADC, and wherein the value of the tunable time interval is stored in a time interval tune register of the SAR ADC.

7. The method of claim 6 , wherein the time interval tune register configures a tunable capacitor of a timer of the SAR ADC.

8. The method of claim 7 , wherein comparing the output signals is performed by a comparator of the SAR ADC, and wherein the timer receives a clock signal from the comparator.

9. The method of claim 6 , wherein the metastability flag register indicates the count of the metastability flags generated during one sample conversion.

10. The method of claim 6 , wherein a signal from a timer of the SAR ADC configures the metastability flag register.

11. A successive approximation register (SAR) analog-to-digital (ADC) converter comprising:
a plurality of switched capacitors configured to sample input signals;
a comparator configured to compare output signals from the plurality of switched capacitors; and
a metastability detector configured to:
determine, based on a value of a tunable time interval, whether to set a respective metastability flag for each bit of a plurality of bits to be evaluated; and
update the value of the tunable time interval based on a count of the metastability flags that have been set.

12. The SAR ADC of claim 11 , further comprising:
a word completion block configured to use the metastability flags for word completion when not all of the plurality of bits have been evaluated,
wherein an output value of the SAR ADC is based on a final value of the SAR and word completion.

13. The SAR ADC of claim 12 , wherein using the metastability flags for word completion comprises:
for each non-evaluated bit of the plurality of bits, assigning a value complementary to the respective non-evaluated bit.

14. The SAR ADC of claim 11 , wherein the count is greater than one, wherein updating the value of the tunable time interval comprises:
increasing the value of the tunable time interval.

15. The SAR ADC of claim 11 , wherein the count is zero, wherein updating the value of the tunable time interval comprises:
decreasing the value of the tunable time interval.

16. The SAR ADC of claim 11 , further comprising:
a metastability flag register configured to store the metastability flags; and
a time interval tune register configured to store the value of the tunable time interval.

17. The SAR ADC of claim 16 , further comprising:
a timer comprising a tunable capacitor that is configured by the time interval tune register.

18. The SAR ADC of claim 17 , wherein the timer receives a clock signal from the comparator.

19. The SAR ADC of claim 16 , wherein the metastability flag register indicates the count of the metastability flags that are generated during one sample conversion.

20. The SAR ADC of claim 16 , further comprising:
a timer configured to output a signal that configures the metastability flag register.

Assignees

• Luxtera Llc

Inventors

• Zabroda Oleksiy

Classifications

• H03M1/1245 Primary

  Details of sampling arrangements or methods · CPC title

• H03M1/125

  Asynchronous, i.e. free-running operation within each conversion cycle · CPC title

• H03M1/42

  Sequential comparisons in series-connected stages with no change in value of analogue signal · CPC title

• H03M1/462

  Details of the control circuitry, e.g. of the successive approximation register · CPC title

• H03M1/468

  in which the input S/H circuit is merged with the feedback DAC array · CPC title