Method and system for providing a variation resistant magnetic junction-based XNOR cell usable in neuromorphic computing

Patent metadata

Field	Value
Publication number	US-11290110-B2
Application number	US-201815886179-A
Country	US
Kind code	B2
Filing date	Feb 1, 2018
Priority date	Oct 26, 2017
Publication date	Mar 29, 2022
Grant date	Mar 29, 2022

Abstract

A hardware cell and method for performing a digital XNOR of an input signal and weights are described. The hardware cell includes input lines, a plurality of pairs of magnetic junctions, output transistors and at least one selection transistor coupled with the output transistors. The input lines receive the input signal and its complement. The magnetic junctions store the weight. Each magnetic junction includes a reference layer, a free layer and a nonmagnetic spacer layer between the reference layer and the free layer. The free layer has stable magnetic states and is programmable using spin-transfer torque and/or spin-orbit interaction torque. The first magnetic junction of a pair receives the input signal. The second magnetic junction of the pair receives the input signal complement. The output transistors are coupled with the magnetic junctions such that each pair of magnetic junctions forms a voltage divider. The output transistors form a sense amplifier.

First claim

We claim:

1. A hardware cell for performing a digital XNOR operation of an input signal with a weight comprising:
a plurality of input lines for receiving the input signal and an input signal complement;
a plurality of pairs of magnetic junctions coupled with the plurality of input lines and storing the weight, each pair of magnetic junctions including a first magnetic junction and a second magnetic junction, each of the first magnetic junction and the second magnetic junction including a reference layer, a free layer and a nonmagnetic spacer layer between the reference layer and the free layer, the free layer having a plurality of stable magnetic states and programmable using at least one of spin-transfer torque (STT) and spin-orbit interaction torque (SOT), the first magnetic junction receiving the input signal, the second magnetic junction receiving the input signal complement;
a plurality of output transistors coupled with the plurality of magnetic junctions such that each pair of magnetic junctions form a voltage divider, the plurality of output transistors forming a sense amplifier; and
at least one selection transistor coupled with the plurality of output transistors.

2. The hardware cell of claim 1 wherein the plurality of output transistors includes a first output transistor and a second output transistor, the first output transistor being connected between the first magnetic junction and the second magnetic junction of the plurality of pairs of magnetic junction and to an XNOR output.

3. The hardware cell of claim 2 wherein the first output transistor has a first source, a first drain and a first gate, the second output transistor has a second source a second drain and a second gate, the first drain being connected between the first magnetic and the second magnetic junction of a first pair of magnetic junctions, the first drain being connected to the second gate of the second output transistor and to the XNOR output, the first gate being connected to the second drain of the second output transistor, the second drain connected between the first magnetic and the second magnetic junction of the second pair of magnetic junctions, the first magnetic junction of the first pair of magnetic junctions storing the weight and the second magnetic junction of the first pair of magnetic junctions storing a weight complement, the first magnetic junction of the second pair of magnetic junctions storing the weight complement, the second magnetic junction of the second pair of magnetic junctions storing the weight.

4. The hardware cell of claim 3 wherein the second drain is connected to an XOR output.

5. The hardware cell of claim 3 wherein the at least one selection transistor includes a single selection transistor having a selection transistor source, a selection transistor gate and a selection transistor drain, the selection transistor drain being coupled with the first source and the second source.

6. The hardware cell of claim 3 wherein the at least one selection transistor includes a first selection transistor and a second selection transistor, the first selection transistor having a first selection transistor source and a first selection transistor drain, the second selection transistor having a second selection transistor source and a second selection transistor gate, the first selection transistor source being connected with the first output transistor drain, the first selection transistor drain being connected between the first magnetic junction and the second magnetic junction of the first pair of magnetic junctions, the second selection transistor source being connected with the second output transistor drain, the second selection transistor drain being connected between the first magnetic junction and the second magnetic junction of the second pair of magnetic junctions.

7. The hardware cell of claim 3 wherein the second pair of magnetic junctions are conventional magnetic junctions and wherein the first pair of magnetic junctions are bottom to up magnetic junctions.

8. The hardware cell of claim 3 further comprising:
a pair of signal lines for providing an input signal value on a first signal line and an input signal complement on a second signal line;
an input stage coupled to the plurality of input lines, to the pair of signal lines and to a supply voltage, the input stage for providing the input signal value and the input signal complement value to the plurality of input lines for a first portion of a time period and for providing a supply voltage to the plurality of input lines for a second portion of the time period.

9. The hardware cell of claim 8 wherein the input stage further includes:
a first multiplexer coupled to the first signal line, the supply voltage and a first input line of the plurality of input lines, the first input line carrying the input signal; and
a second multiplexer coupled to the second signal line, the supply voltage and a second input line of the plurality of input lines, the second input line carrying the input signal complement.

10. The hardware cell of claim 1 wherein the nonmagnetic spacer layer is a tunneling barrier layer.

11. A neural network comprising:
a plurality of XNOR cells, each of the plurality of XNOR cells for performing a digital XNOR operation of an input signal with a weight, each of the plurality of XNOR cells including a pair of input lines, a plurality of pairs of magnetic junctions coupled with the plurality of input lines, a plurality of output transistors and at least one selection transistor, the pair of input lines for receiving the input signal and an input signal complement, the plurality of pairs of magnetic junctions coupled with the plurality of input lines and storing the weight, each pair of magnetic junctions including a first magnetic junction and a second magnetic junction, each of the first magnetic junction and the second magnetic junction including a reference layer, a free layer and a nonmagnetic spacer layer between the reference layer and the free layer, the free layer having a plurality of stable magnetic states and programmable using at least one of spin-transfer torque (STT) and spin-orbit interaction torque (SOT), the first magnetic junction receiving the input signal, the second magnetic junction receiving the input signal complement, the plurality of output transistors being coupled with the plurality of magnetic junctions such that each pair of magnetic junctions form a voltage divider, the plurality of output transistors forming a sense amplifier, the at least one selection transistor coupled with the plurality of output transistors; and
a plurality of lines coupling the plurality of XNOR cells.

12. The neural network of claim 11 wherein the plurality of output transistors includes a first output transistor and a second output transistor, the first output transistor having a first source, a first drain and a first gate, the second output transistor having a second source a second drain and a second gate, the first drain being connected between the first magnetic and the second magnetic junction of a first pair of magnetic junctions, the first drain being connected to the second gate of the second output transistor and to the XNOR output, the first gate being connected to the second drain of the second output transistor, the second drain connected between the first magnetic and the second magnetic junction of the second pair of magnetic junctions, the first magnetic junction of the first pair of magnetic junctions storing the weight and the second magnetic junction of the first pair of magnetic junctions storing a weight complement, the first magnetic junction of the second pair of magnetic

Assignees

• Samsung Electronics Co Ltd

Inventors

• Obradovic Borna J
• Rakshit Titash
• Hatcher Ryan M
• Kittl Jorge A
• Rodder Mark S

Classifications

• G06N3/063 Primary

  using electronic means · CPC title

• H03K19/18

  using galvano-magnetic devices, e.g. Hall-effect devices · CPC title

• G11C13/0002

  using resistive RAM [RRAM] elements · CPC title

• H03K19/215 Primary

  using field-effect transistors · CPC title

• H10N50/10

  Magnetoresistive devices · CPC title