Positive logic digitally tunable capacitor

Patent metadata

Field	Value
Publication number	US-11290087-B2
Application number	US-201916653728-A
Country	US
Kind code	B2
Filing date	Oct 15, 2019
Priority date	Sep 2, 2016
Publication date	Mar 29, 2022
Grant date	Mar 29, 2022

Abstract

Methods and devices providing Positive Logic biasing schemes for use in a digitally tuning capacitor in an integrated circuit device are described. The described methods can be used in integrated circuits with stringent requirements in terms of switching time, power handling, noise sensitivity and power consumption. The described devices include DC blocking capacitors arranged in series with stacked switches coupled to RF nodes. The stacked FET switches receive non-negative supply voltages through their drains and gates during the ON and OFF states to adjust the capacitance between the two nodes.

First claim

What is claimed is:

1. An integrated circuit block comprising:
a first node;
a second node;
a resistive network;
a series arrangement of two or more capacitors and a plurality of FET switches coupled between the first node and the second node;
supply rails providing a first supply rail voltage and a second supply rail voltage, and
a first control voltage and a second control voltage;
wherein:
a first capacitor of the two or more capacitors is coupled to the first node and a second capacitor of the two or more capacitors is coupled to the second node;
the plurality of FET switches comprises a first end FET switch and a second end FET switch, the first end FET switch being closest to the first node and farthest from the second node and the second end FET switch being closest to the second node and farthest from the first node;
each FET switch comprises a gate resistor coupling a FET switch gate to the first control voltage;
the resistive network coupling the FET switch sources of the plurality of FET switches and/or FET switch drains of the plurality of FET switches to the second control voltage;
the first control voltage and the second control voltage are non-negative voltages configured to enable and disable the FET switches and thereby adjusting a capacitance between the first node and the second node, and
the second control voltage is a constant mid rail voltage regardless of ON or OFF states of the plurality of FET switches.

2. The integrated circuit block of claim 1 , wherein the mid rail voltage is at least one FET switch threshold voltage above the first supply voltage and at least one FET switch threshold voltage below the second supply voltage.

3. The integrated circuit block of claim 2 , wherein the first control voltage is switched between the first supply rail voltage and the second supply rail voltage to facilitate switching of the FET switches to the ON or OFF states.

4. The integrated circuit block of claim 1 , wherein at least one of drain and/or source of the plurality of FET switches is not directly connected to the resistive network.

5. The integrated circuit block of claim 1 , wherein the plurality of FET switches are four terminal FETs, a body of the four terminal FETs being connected to ground.

6. The integrated circuit block of claim 1 , wherein the plurality of FET switches are four terminal FETs, a body of the four terminal FETs being connected to a supply voltage through a plurality of resistors.

7. The integrated circuit block of claim 1 , wherein the two or more capacitors have same capacitances.

8. The integrated circuit block of claim 1 , wherein the first control voltage and the second control voltage are configured such that a voltage across gate-source terminals of the FET switches is smaller or equal to a maximum allowable voltage level.

9. A digitally tunable capacitor (DTC) circuit comprising:
a plurality of the integrated circuit blocks of claim 1 , wherein the plurality of integrated circuit blocks are configured in parallel.

10. The DTC of claim 9 , wherein the first control voltage has a same first voltage level for each integrated circuit block of the plurality of integrated circuit blocks and the second control voltage has a same second voltage level for each integrated circuit block of the plurality of integrated circuit blocks.

11. The integrated circuit block of claim 1 , wherein the plurality of resistors have same resistances.

12. The integrated circuit block of claim 1 , wherein the plurality of FET switches comprises two or more FET switches configured to withstand a voltage greater than a voltage withstood by one switch.

13. The integrated circuit block of claim 1 , wherein the non-negative control voltages are positive control voltages regardless of states of the plurality of FET switches.

14. The integrated circuit block of claim 1 implemented on a silicon-on-insulator (SOI) chip.

15. An integrated circuit comprising:
a first node;
a second node;
a series arrangement of two or more capacitors and a plurality of FET switches; the plurality of FET switches comprising a first end FET switch and a second end FET switch, the first end FET switch being the closest to the first node and farthest from the second node and the second end FET switch being closest to the second node and farthest from the first node, and each of the plurality of FET switches comprising a gate resistor;
a non-negative second supply voltage independent of a number of FET switches of the plurality of FET switches, the non-negative second supply voltage being a constant mid rail voltage;
a resistive network, the resistive network coupling the drains and/or sources of the plurality of FET switches to the second supply voltage regardless of ON and OFF states of the plurality of FET switches, and
a non-negative first supply voltage independent of a number of FET switches of the plurality of FET switches connecting the gate of each of the FET switches from the plurality of the FET switches to the first supply voltage via a corresponding gate resistor;
wherein:
the series arrangement of the two or more capacitors and the plurality of FET switches are coupled between the first and the second nodes;
a first capacitor and a second capacitor of the two or more capacitors are coupled to the first node and the second node respectively, and
the first and the second supply voltage are configured to enable or disable the FET switches to adjust a capacitance between the first node and the second node.

16. A method of digitally tuning a capacitor in an integrated circuit, the method comprising the steps of:
providing a first node;
providing a second node;
providing a series arrangement of two or more capacitors and a plurality of FET switches; the plurality of FET switches comprising a first end FET switch and a second end FET switch, the first end FET switch being the closest to the first node and farthest from the second node and the second end FET switch being closest to the second node and farthest from the first node, and each of the plurality of FET switches comprising a gate resistor;
providing a non-negative second supply voltage independent of a number of FET switches of the plurality of FET switches, the non-negative second supply voltage being a constant mid rail voltage;
providing a resistive network, the resistive network coupling the drains and/or sources of the plurality of FET switches to the second supply voltage regardless of ON and OFF states of the plurality of FET switches;
providing a non-negative first supply voltage independent of a number of FET switches of the plurality of FET switches connecting the gate of each of the FET switches from the plurality of the FET switches to the first supply voltage via a corresponding gate resistor;
coupling the series arrangement of two or more capacitors and the plurality of FET switches between the first node and the second node;
coupling a first capacitor of the two or more capacitors to the first node and coupling a second capacitor of the two or more capacitors to the second node; and
enabling or disabling the FET switches using the first supply voltage and the second supply voltage and thereby adjusting a capacitance between the first node and the second node.

17. A digitally tunable capacitor circuit comprising a plurality of integrated circuit blocks configured in parallel, wherein an integrated circuit block of the plurality of integrated circuit blocks comprises:
a first node;
a second node;
a resistive network;
a series arrangement of two or more capacitors

Assignees

• Psemi Corp

Inventors

• Ranta Tero Tapio

Classifications

• H03J5/24 Primary

  with a number of separate pretuned tuning circuits or separate tuning elements selectively brought into circuit, e.g. for waveband selection or for television channel selection · CPC title

• H03K17/687

  the devices being field-effect transistors · CPC title

• H03B2201/0208

  the means being an element with a variable capacitance, e.g. capacitance diode · CPC title

• H03J3/20

  of single resonant circuit by varying inductance only or capacitance only · CPC title

• H03B2201/0266

  the means comprising a transistor · CPC title