Method for controlling a semiconductor bridge of an electrically operable motor by means of a ramp signal, control device and arrangement

Patent metadata

Field	Value
Publication number	US-11290041-B2
Application number	US-201816754605-A
Country	US
Kind code	B2
Filing date	Oct 1, 2018
Priority date	Oct 13, 2017
Publication date	Mar 29, 2022
Grant date	Mar 29, 2022

Abstract

A method for controlling a semiconductor bridge of an electrically operable motor, the semiconductor bridge being controlled depending on a pulse width modulation signal by a first controllable semiconductor switch and a separate second controllable semiconductor switch for supplying the electrically operable motor with electrical energy, a ramp signal with a predeterminable ramp slope for controlling one of the two controllable semiconductor switches being generated by a ramp generator, depending on the pulse width modulation signal. The invention also relates to a control device and to an arrangement.

First claim

The invention claimed is:

1. A method for controlling a semiconductor bridge of an electrically operable motor, the semiconductor bridge being controlled including a first controllable semiconductor switch and a separate second controllable semiconductor switch for supplying the electrically operable motor with electrical energy, the method comprising:
outputting, by a controller, based on a pulse width modulation signal, a control signal to generate a ramp signal;
generating, by a ramp generator, in response to the control signal output by the controller, the ramp signal with a predeterminable ramp slope for controlling the first controllable semiconductor switch;
applying, by the controller, the control signal to the second controllable semiconductor switch; and
applying, by the ramp generator, the ramp signal to the first controllable semiconductor switch,
wherein the predeterminable ramp slope is determined by the controller to ensure that the first controllable semiconductor switch:
closes after the second controllable semiconductor switch opens, and
opens before the second controllable semiconductor switch closes.

2. The method as claimed in claim 1 ,
wherein
the ramp signal for a predetermined opening value represents an opening signal for the first controllable semiconductor switch and a closing signal for the second controllable semiconductor switch when the first controllable semiconductor switch is open.

3. The method as claimed in claim 2 ,
wherein
the ramp signal is generated by the ramp generator with a predetermined fall time, so that the closing signal for the second controllable semiconductor switch is at least only generated after the fall time.

4. The method as claimed in claim 3 ,
wherein
the closing signal for the second controllable semiconductor switch is only generated after the fall time and after a predetermined fade-out time.

5. The method as claimed in claim 1 , wherein
an opening signal for the second controllable semiconductor switch is generated when there is a predetermined opening value of the pulse width modulation signal and a closing signal for the first controllable semiconductor switch is generated when the second controllable semiconductor switch is open.

6. The method as claimed in claim 5 ,
wherein
the ramp signal for the first controllable semiconductor switch is generated with a predetermined rise time when the second controllable semiconductor switch is open.

7. The method as claimed in claim 1 , wherein
the ramp signal is amplified by a voltage follower.

8. The method as claimed in claim 1 , wherein
the fall time and/or the rise time of the ramp signal and/or the fade-out time is predetermined by an input device.

9. The method as claimed in claim 1 , wherein
a first switching voltage of the ramp signal for the first controllable semiconductor switch and a second switching voltage for the second controllable semiconductor switch are monitored.

10. The method as claimed in claim 1 , wherein
the pulse width modulation signal is output by a microcontroller to the controller.

11. A control device which is designed to carry out a method for controlling a semiconductor bridge of an electrically operable motor, the semiconductor bridge being controlled including a first controllable semiconductor switch and a separate second controllable semiconductor switch for supplying the electrically operable motor with electrical energy, the control device comprising:
a controller configured to output based on a pulse width modulation signal, a control signal to generate a ramp signal; and
a ramp generator configured to generate in response to the control signal output by the controller, the ramp signal with a predeterminable ramp slope for controlling the first controllable semiconductor switch;
wherein the controller is further configured to apply the control signal to the second controllable semiconductor switch,
wherein the ramp generator is further configured to apply the ramp signal to the first controllable semiconductor switch,
wherein the predeterminable ramp slope is determined by the controller to ensure that the first controllable semiconductor switch:
closes after the second controllable semiconductor switch opens, and
opens before the second controllable semiconductor switch closes.

12. The control device as claimed in claim 11 , wherein the pulse width modulation signal is output by a microcontroller to the controller.

13. The control device as claimed in claim 12 ,
wherein the first controllable semiconductor switch is connected as a high-side switch and the second controllable semiconductor switch is connected as a low-side switch, and the first controllable semiconductor switch is controlled by the ramp signal.

Assignees

• Conti Temic Microelectronic Gmbh

Inventors

• Joos Uli

Classifications

• H03K17/063

  in field-effect transistor switches · CPC title

• H02P7/29

  using pulse modulation · CPC title

• H03K17/163 Primary

  Soft switching · CPC title

• H03K17/162

  without feedback from the output circuit to the control circuit · CPC title

• H03K17/00

  Electronic switching or gating, i.e. not by contact-making and –breaking (gated amplifiers H03F3/72; switching arrangements for exchange systems using static devices H04Q3/52) · CPC title