Inductive load driver slew rate controller

Patent metadata

Field	Value
Publication number	US-9312852-B2
Application number	US-201414200266-A
Country	US
Kind code	B2
Filing date	Mar 7, 2014
Priority date	Mar 9, 2013
Publication date	Apr 12, 2016
Grant date	Apr 12, 2016

Abstract

A circuit and method for digital controlling the slew rate of load voltage are provided. The circuit is comprised of a digital slew-rate control unit that utilizes a feedback signal to generate control signals where the feedback signal indicates the observed rate of voltage change on the load. The circuit is further comprised of a load driver circuit that is operated by the control signals and provides a slew-rate controlled output voltage used to operate a load switch, where the load switch provides power to the load. The circuit is configured to operate the load switch using a slew-rate controlling driver, depending on the state of the load switch transition, and a non-controlling driver.

First claim

What is claimed is:

1. An integrated circuit for driving a first load switch wherein the first load switch powers a current load, the integrated circuit comprising:
a first digital slew-rate control unit for generating control signals, wherein the first digital slew-rate control unit receives a first input signal and generates first control signals based on the first input signal and a feedback signal that indicates the rate of voltage change on the load; and
a first load driver circuit operated by the first control signals and the first input signal, wherein the first load driver circuit comprises a large low impedance driver receiving said first control signals and a small current limited driver receiving said first input signal, wherein an output of the large low impedance driver is coupled with the output of the small current limited driver to generate a slew-rate controlled first output voltage for operating the first load switch.

2. The integrated circuit of claim 1 , wherein the first load switch is a MOSFET.

3. The integrated circuit of claim 2 ,
wherein the small current limited driver generates a constant output during state transitions of the load switch while the large low impedance driver is inactive and wherein upon completed state transition, the large low impedance driver is activated.

4. A circuit arrangement comprising the integrated circuit according to claim 3 , further comprising a low side MOSFET coupled with ground and a high side MOSFET coupled with a supply voltage and in series with the low side MOSFET, the low side and high side MOSFETs receiving the slew-rate controlled first and second output voltages, respectively, wherein the low side and high side MOSFETs each form the first and second load switch, respectively.

5. The integrated circuit of claim 1 , further comprising:
a second digital slew-rate control unit for generating control signals, wherein the second digital slew-rate control unit receives a second input signal and generates second control signals based on the feedback signal that indicates the rate of voltage change on the load; and
a second load driver circuit operated by the second control signals and the second input signal, wherein the second load driver circuit comprises a large low impedance driver receiving said second control signals and a small current limited driver receiving said second input signal, wherein an output of the large low impedance driver is coupled with the output of the small current limited driver to generate a slew-rate controlled second output voltage that operates a second load switch coupled in series with said first load switch.

6. The integrated circuit of claim 5 , wherein the second digital slew-rate control unit comprises:
a capacitor that receives a supply voltage; and
a resistor coupled in series with the capacitor that defines the slew rate, wherein the resistor receives the feedback voltage;
wherein the second digital slew-rate control unit further comprises:
a NAND gate having a first input receiving the feedback signal and a second input receiving an input voltage signal, wherein the output of the NAND gate controls a p-channel field-effect transistor of the second load driver circuit; and
a NOR gate having a first input receiving the feedback signal and a second input receiving the input voltage signal, wherein the output of the NOR gate controls an n-channel field-effect transistor of the second load driver circuit, wherein the p-channel field-effect transistor and the re-channel field-effect transistor are coupled in series and a node between the p-channel field-effect transistor and the n-channel field-effect transistor provides an output of the second load driver circuit.

7. The integrated circuit of claim 1 , wherein the first digital slew-rate control unit comprises:
a capacitor that receives the feedback signal; and
a resistor coupled with the capacitor that defines the slew rate.

8. The integrated circuit of claim 7 , wherein the first digital slew-rate control unit further comprises:
a NAND gate having a first input receiving the feedback signal and a second input receiving an input voltage signal, wherein the output of the NAND gate controls a p-channel field-effect transistor of the first load driver circuit; and
a NOR gate having a first input receiving the feedback signal and a second input receiving the input voltage signal, wherein the output of the NOR gate controls an n-channel field-effect transistor of the first load driver circuit, wherein the p-channel field-effect transistor and the re-channel field-effect transistor are coupled in series and a node between the p-channel field-effect transistor and the n-channel field-effect transistor provides an output of the first load driver circuit.

9. A circuit arrangement comprising the integrated circuit according to claim 1 , further comprising the first load switch, wherein the first load switch is a MOSFET receiving the slew-rate controlled first output voltage.

10. A circuit arrangement comprising the integrated circuit according to claim 1 , further comprising the first load switch, wherein the first load switch is a low side MOSFET coupled with ground receiving the slew-rate controlled first output voltage and a high side MOSFET coupled with a supply voltage and in series with the low side MOSFET.

11. A slew-rate controlled load driving system comprising:
a first and second load switch coupled in series for powering a current load connected to a node between the first and second load switch;
a first digital slew-rate control unit that generates control signals, wherein the control signals are generated based on a feedback signal that indicates the rate of voltage change on the load;
a first load driver circuit operated by the first control signals and the first input signal, wherein the first load driver circuit comprises a large low impedance driver receiving said first control signals and a small current limited driver receiving said first input signal, wherein an output of the large low impedance driver is coupled with the output of the small current limited driver to generate a slew-rate controlled first output voltage for operating the first load switch,
a second digital slew-rate control unit for generating control signals, wherein the second digital slew-rate control unit receives a second input signal and generates second control signals based on the feedback signal that indicates the rate of voltage change on the load; and
a second load driver circuit operated by the second control signals and the second input signal, wherein the second load driver circuit comprises a large low impedance driver receiving said second control signals and a small current limited driver receiving said second input signal, wherein an output of the large low impedance driver is coupled with the output of the small current limited driver to generate a slew-rate controlled second output voltage that operates a second load switch coupled in series with said first load switch.

12. The system of claim 11 , wherein the first and second load switches are MOSFETs.

13. The system of claim 12 , wherein each small current limited driver generates a constant output during state transitions of the first or second load switch while the large low impedance driver is inactive and wherein upon completed state transition, the large low impedance driver is activated.

14. The system of claim 11 , wherein first load switch is a low-side driver, and the second load switch is a high-side driver.

15. The system of claim 11 , wherein the first digital slew-rate control unit further compr

Assignees

• Microchip Tech Inc

Inventors

• De Geeter Bart
• Furrer Nicolas

Classifications

• H03K5/04 Primary

  by increasing duration; by decreasing duration · CPC title

• H03K17/6871 Primary

  the output circuit comprising more than one controlled field-effect transistor · CPC title

• H03K2217/0072

  Low side switches, i.e. the lower potential [DC] or neutral wire [AC] being directly connected to the switch and not via the load · CPC title

• H03K17/166

  Soft switching · CPC title

• H03K2217/0063

  High side switches, i.e. the higher potential [DC] or life wire [AC] being directly connected to the switch and not via the load · CPC title