Semiconductor device including carrier injection layers

Patent metadata

Field	Value
Publication number	US-11289476-B2
Application number	US-202016833977-A
Country	US
Kind code	B2
Filing date	Mar 30, 2020
Priority date	Nov 16, 2017
Publication date	Mar 29, 2022
Grant date	Mar 29, 2022

Abstract

In a semiconductor device in which an IGBT region having an IGBT element and an FWD region having an FWD element are formed to a semiconductor substrate, a plurality of carrier injection layers electrically connected with a second electrode and configuring a PN junction with a field stop layer is disposed in a cathode layer. When an impurity concentration of the field stop layer is defined as Nfs [cm−3], and a length of a shortest portion of each of the plurality of carrier injection layers along a planar direction of the semiconductor substrate is defined as L1 [μm], the plurality of carrier injection layers satisfies a relationship of L1>6.8×10−16×Nfs+20.

First claim

What is claimed is:

1. A semiconductor device comprising:
a drift layer of a first conductivity type configured by a semiconductor substrate and having a first surface and a second surface opposite to each other;
a base layer of a second conductivity type disposed on the first surface of the drift layer;
an emitter region of the first conductivity type disposed in a surface layer portion of the base layer apart from the drift layer across the base layer, the emitter region having an impurity concentration higher than an impurity concentration of the drift layer;
a gate insulating film disposed on a surface of the base layer located between the emitter region and the drift layer;
a gate electrode disposed on the gate insulating film;
a field stop layer of the first conductivity type disposed on the second surface of the drift layer opposite from the base layer, and having an impurity concentration higher than the impurity concentration of the drift layer;
a collector layer of the second conductivity type disposed on a surface of the field stop layer opposite from the drift layer;
a cathode layer of the first conductivity type disposed on the surface of the field stop layer opposite from the drift layer, and being adjacent to the collector layer;
a first electrode electrically connected to the base layer and the emitter region;
a second electrode electrically connected to the collector layer and the cathode layer; and
a plurality of carrier injection layers of the second conductivity type disposed in the cathode layer, electrically connected to the second electrode, and configuring a PN junction with the field stop layer, wherein in the semiconductor device, a region in which the collector layer is disposed is defined as an insulated gate bipolar transistor (IGBT) region having an IGBT element, and a region in which the cathode layer is disposed is defined as a free-wheel diode (FWD) region having an FWD element, and when an impurity concentration of the field stop layer is defined as Nfs [cm.sup.-3],
a length of a shortest portion of each of the plurality of carrier injection layers along a planar direction of the semiconductor substrate is defined as L 1 [μm], and a length of a portion of the cathode layer located between adjacent two of the plurality of carrier injection layers is defined as L 2 [μm], the plurality of carrier injection layers satisfies a relationship of L 2 >L 1 >6.8×10.sup.-16×Nfs+20.

2. The semiconductor device according to claim 1 , wherein when a sum of thicknesses of the drift layer and the field stop layer is defined as a reference thickness, the length of a portion of the cathode layer located between adjacent two of the plurality of carrier injection layers is less than twice the reference thickness.

3. The semiconductor device according to claim 1 , wherein
the IGBT region and the FWD region extend along a first direction as a longitudinal direction, and are alternately arranged in a second direction intersecting with the first direction, and
the plurality of carrier injection layers extend along the second direction.

Assignees

• Denso Corp

Inventors

• Murakawa Koichi
• Takahashi Shigeki
• Sumitomo Masakiyo

Classifications

• H10D84/811

  Combinations of field-effect devices and one or more diodes, capacitors or resistors · CPC title

• H10D8/00 Primary

  Diodes (variable-capacitance diodes H10D1/64; gated diodes H10D12/00) · CPC title

• H10D62/129

  Cathode regions of diodes · CPC title

• H10D62/393

  Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title

• H10D62/142

  Anode regions of thyristors or collector regions of gated bipolar-mode devices · CPC title