Electrical mask validation

Patent metadata

Field	Value
Publication number	US-11288429-B2
Application number	US-202016732824-A
Country	US
Kind code	B2
Filing date	Jan 2, 2020
Priority date	Nov 30, 2017
Publication date	Mar 29, 2022
Grant date	Mar 29, 2022

Abstract

An embodiment of the invention may include a method for ensuring semiconductor design integrity. The method may include analyzing a photomask design for a semiconductor circuit. The photomask may include a primary electrical design necessary for the operation of the semiconductor circuit, and white space, which has no primary electrical design. The method may include inserting a secondary electrical design into the white space of the photomask design for the semiconductor circuit. The secondary electrical design may have known electrical properties for validating the semiconductor circuit design.

First claim

What is claimed is:

1. A method for ensuring semiconductor design integrity, the method comprising:
analyzing one or more deposition layer designs for one or more semiconductor chips, the deposition layer design having one or more circuit designs for one or more semiconductor chips and a kerf between the one or more circuit designs for the one or more semiconductor chips, the one or more circuit designs for the one or more semiconductor chips having a primary electrical design necessary for the operation of the one or more semiconductor chips, and white space within the primary electrical design, wherein the white space has no primary electrical design; and
inserting a secondary electrical circuit design into the white space of the one or more circuit designs for the one or more semiconductor chips, wherein the secondary electrical circuit design has one or more known testable electrical properties for validating the one or more semiconductor chips.

2. The method as in claim 1 , wherein inserting a secondary electrical circuit design into the white space of the one or more circuit designs for the one or more semiconductor chips, further comprises:
inserting a different secondary electrical design into the white space of each of the one or more deposition layer designs, wherein each different secondary electrical design has one or more different known testable electrical properties for validating the one or more semiconductor chips.

3. The method as in claim 1 , further comprising:
building the one or more semiconductor chips according to the one or more deposition layer designs, the one or more semiconductor chips having a primary electrical circuit and a secondary electrical circuit;
analyzing the one or more semiconductor chips for the one or more known electrical properties of the secondary electrical circuit;
comparing the electrical properties of the secondary electrical circuit of the one or more semiconductor chips to the one or more known electrical properties of the secondary electrical circuit; and
validating the one or more semiconductor chips when the secondary electrical circuit and the one or more known electrical properties of the secondary electrical circuit match.

4. The method as in claim 2 , further comprising:
building the one or more semiconductor chips according to the one or more deposition layer designs, the one or more semiconductor chips having a primary electrical circuit and one or more different secondary electrical circuits;
analyzing the one or more semiconductor chips for the one or more known electrical properties of the different secondary electrical circuits at each deposition layer;
comparing the electrical properties of each of the different secondary electrical circuits of the one or more semiconductor chips to the one or more known electrical properties of each of the different secondary electrical circuits; and
validating the one or more semiconductor chips when each of the different secondary electrical circuits and the one or more known electrical properties of each of the different secondary electrical circuit match.

5. The method as in claim 3 , further comprising:
discarding the one or more semiconductor chips when the secondary electrical circuit and the one or more known electrical properties of the secondary electrical circuit do not match.

6. The method as in claim 4 , further comprising:
discarding the one or more semiconductor chips when one or more of the different secondary electrical circuits and the one or more known electrical properties of the different secondary electrical circuits do not match.

7. The method as in claim 1 , wherein the one or more known electrical properties of the secondary circuit design is of at least one of the group consisting of: a design resistance, a design capacitance, and a design inductance.

8. The method as in claim 1 , wherein the secondary electrical design is electrically isolated from the primary electrical design.

9. The method as in claim 1 , wherein the secondary electrical design is electrically coupled to the primary electrical design.

10. The method as in claim 1 , further comprising:
enhancing the one or more deposition layer designs using optical proximity correction.

11. A semiconductor structure comprising:
a primary electrical circuit necessary for the operation of the semiconductor structure, and white space within the primary electrical circuit, wherein the white space has no primary electrical circuit; and
a secondary electrical circuit formed in the white space of the primary electrical circuit, wherein the secondary electrical circuit has one or more known electrical properties for validating the semiconductor structure.

12. The semiconductor structure of claim 11 , wherein the secondary electrical circuit has interconnects between at least two deposition layers of the semiconductor structure.

13. The semiconductor structure of claim 11 , wherein the secondary electrical circuit is electrically coupled to the primary electrical circuit.

14. The semiconductor structure of claim 11 , wherein the secondary electrical circuit is electrically isolated from the primary electrical circuit.

15. The semiconductor structure of claim 11 , wherein the one or more known electrical properties of the secondary circuit is of at least one of the group consisting of: a design resistance, a design capacitance, and a design inductance.

16. A semiconductor structure comprising:
one or more deposition layers;
a primary electrical circuit necessary for the operation of the semiconductor structure, and white space within the primary electrical circuit, wherein the white space has no primary electrical circuit; and
a plurality of secondary electrical circuits formed in the white space of the primary electrical circuit, wherein the secondary electrical circuit has one or more known electrical properties for validating the semiconductor structure.

17. The structure of claim 16 , wherein the plurality of secondary electrical circuits further comprises:
a secondary electrical circuit formed on each of the one or more deposition layers of the semiconductor structure, each of the one or more deposition layers of the semiconductor structure containing a different secondary electrical circuit with one or more different known electrical properties for validating the semiconductor circuit design.

18. The structure of claim 17 , wherein each of the different secondary electrical circuits are electrically coupled to the primary electrical circuit.

19. The structure of claim 17 , wherein each of the different secondary electrical circuits are electrically isolated from the primary electrical circuit.

20. The structure of claim 16 , wherein the one or more known electrical properties of the secondary circuit is of at least one of the group consisting of: a design resistance, a design capacitance, and a design inductance.

Assignees

• IBM

Inventors

• Corliss Daniel
• Dunn Derren N
• Guillorn Michael A
• Fetterolf Shawn P

Classifications

• H10P76/00

  Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography · CPC title

• H10W42/00

  Arrangements for protection of devices (arrangements for thermal protection H10W40/00) · CPC title

• G06F30/333 Primary

  Design for testability [DFT], e.g. scan chain or built-in self-test [BIST] · CPC title

• G06F2115/10

  Processors · CPC title

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title