Techniques for performing a non-blocking control sync operation

US11288201B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11288201-B2
Application numberUS-201916287336-A
CountryUS
Kind codeB2
Filing dateFeb 27, 2019
Priority dateFeb 23, 2017
Publication dateMar 29, 2022
Grant dateMar 29, 2022

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An apparatus includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller includes an interface configured to send first data to be stored to the non-volatile memory. The controller further includes a control circuit configured to generate updated control information based on storing of the first data to the non-volatile memory. The interface is further configured to concurrently send second data and the updated control information to be stored at the non-volatile memory. The non-volatile memory is configured to store the second data and the updated control information in a non-blocking manner

First claim

Opening claim text (preview).

What is claimed is: 1. A method of operation of a non-blocking control sync operation in a data storage device, comprising: detecting, by a controller, a trigger event for the non-blocking control sync operation for user data, wherein the trigger event is determined by reaching a threshold time duration, wherein the threshold time duration comprises a time since previously updating and storing control information; detecting a trigger event for the non-blocking control sync operation; when the trigger event is detected, creating the log file that includes control information updates which correspond to processed memory commands, wherein creating the log file comprises generating a mapping table of the updated control information; providing, by the controller, barrier commands to a plurality of command queues of the data storage device; generating, by a control circuit, an indication as a response to detecting the trigger event; providing, by a flash translation layer (FTL), the indication to a plurality of processors; generating, by the plurality of processors, a barrier command, wherein the barrier command propagates through all of the plurality of command queues until reaching the one or more memory dies; propagating the barrier commands through all of the plurality of command queues; accumulating, by the controller, response messages for completion of the barrier commands from all of the plurality of command queues of the data storage device; sending, by the controller, a log file including a mapping table data to one or more memory dies maintaining a coherence of data and control information; and writing the user data and the log file to the one or more memory dies continuously during the non-blocking control sync operation. 2. The method of claim 1 , further comprising: transmitting a set of memory commands to all of the plurality of command queues after providing the barrier command, wherein the set of memory commands are written to the one or more memory dies continuously including during the non-blocking control sync operation. 3. The method of claim 1 , further comprising: setting a threshold according to a number of all of the plurality of command queues; receiving, by the controller, one or more completion messages; adjusting a value indicated by a counter in response to receiving each of one or more completion messages; comparing the value to the threshold to determine a number satisfies the threshold; when a number of the one or more completion messages satisfies the threshold, sending the log file to the one or more memory dies; and writing the log file to the one or more memory dies. 4. The method of claim 1 , further comprising: providing a plurality of processors, wherein each processor of the plurality of processors provides the barrier command propagated through all of the plurality of command queues, wherein the barrier command has corresponding barrier identification and threshold numbers. 5. The method of claim 1 , further comprising: collecting messages from all of the plurality of command queues for adjusting a plurality of counter values. 6. The method of claim 1 , further comprising: providing multiple number of die managers, wherein each die manager is configured to receive messages from a die and increment a counter. 7. A method of operation of a data storage device, comprising: sending, by a controller, first data to a non-volatile memory of the data storage device; storing the first data at the non-volatile memory of the data storage device; detecting, by a controller, a trigger event, wherein the trigger event corresponds with a threshold time duration, wherein the threshold time duration comprises a time since previously updating and storing control information; providing, by a flash translation layer (FTL), an indication to a plurality of processors, wherein the plurality of processors generates a barrier command, and wherein the controller sends the barrier command to the non-volatile memory to be executed; generating, by the controller, an updated control information based on the storing of the first data to the non-volatile memory, wherein the generated updated control information includes a mapping table; in response to the sending of the first data to the non-volatile memory, generating, by the controller, an updated mapping table; after generating the updated mapping table and executing the barrier command, concurrently sending, by the controller, the updated mapping table and second data to the non-volatile memory; and storing, by the controller, the updated mapping table and the second data in a non-blocking operation. 8. The method of claim 7 , wherein the second data is sent to the non-volatile memory to initiate a write operation. 9. The method of claim 7 , wherein the updated mapping table is sent to the non-volatile memory to initiate a non-blocking control sync (CS) operation. 10. The method of claim 7 , further comprising: receiving a completion acknowledgment in response to sending the first data, wherein the updated mapping table is generated in response to the completion acknowledgement.

Assignees

Inventors

Classifications

  • G06F3/0613Primary

    in relation to throughput · CPC title

  • management of metadata or control data · CPC title

  • Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

  • in block erasable memory, e.g. flash memory · CPC title

  • Management of blocks · CPC title

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What does patent US11288201B2 cover?
An apparatus includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller includes an interface configured to send first data to be stored to the non-volatile memory. The controller further includes a control circuit configured to generate updated control information based on storing of the first data to the non-volatile memory. The interface is further con…
Who is the assignee on this patent?
Western Digital Tech Inc
What technology area does this patent fall under?
Primary CPC classification G06F3/0613. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Mar 29 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).