Operating method of memory system and host recovering data with write error

US11288183B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11288183-B2
Application numberUS-202016858959-A
CountryUS
Kind codeB2
Filing dateApr 27, 2020
Priority dateOct 4, 2019
Publication dateMar 29, 2022
Grant dateMar 29, 2022

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  1. Title

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  2. Abstract

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  5. First independent claim

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Abstract

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A method of operating a memory system including a memory device, including in response to a write request of a host, storing write data and a physical address received from the host in a buffer; performing a write operation on the memory device based on the write data and the physical address; based on a write error corresponding to the write data occurring, asynchronously providing the host with error occurrence information; and providing the host with the write data having the write error and information used for a recovery from the write error.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of operating a memory system comprising a memory device, the method comprising: in response to a write request of a host, storing write data and a physical address received from the host in a buffer; performing a write operation on the memory device based on the write data and the physical address; based on a write error corresponding to the write data occurring, asynchronously providing the host with error occurrence information, wherein the error occurrence information is registered in an error processing wait list by the host; and providing the host with the write data having the write error and information used for a recovery from the write error. 2. The method of claim 1 , wherein the performing of the write operation comprises: based on the write data, generating at least one parity comprising at least one of an error correcting code (ECC) parity of the write data or a recovery parity of pieces of write data in a recovery unit corresponding to the write data; and writing the write data and the generated at least one parity. 3. The method of claim 2 , wherein the information used for the recovery from the write error comprises at least one of the at least one parity, normal data included in the recovery unit, or management information of the memory system. 4. The method of claim 1 , wherein, based on the write error occurring in a data area, the information used for the recovery from the write error comprises metadata corresponding to the write data having the write error. 5. The method of claim 1 , wherein the write data having the write error and the information used for the recovery from the write error are provided to the host based on a request for the information used for the recovery from the write error being received from the host. 6. The method of claim 1 , wherein the error occurrence information comprises the physical address of the write data having the write error. 7. The method of claim 1 , wherein the providing of the host with the write data having the write error and the information used for the recovery from the write error comprises storing the write data having the write error and the information used for the recovery from the write error in one of a controller memory buffer (CMB) included in the memory system or a host memory buffer (HMB) included in the host. 8. The method of claim 7 , further comprising providing the host with a return signal based on the storing. 9. A method of operating a host configured to control a memory system, the method comprising: based on write data and a physical address, transmitting a first write request to the memory system; asynchronously acquiring, from the memory system, error occurrence information about a write error corresponding to the write data occurring in the memory system; registering the error occurrence information in an error processing wait list; acquiring the error occurrence information from the error processing wait list; acquiring the write data having the write error and information used for a recovery from the write error from the memory system; based on the write data having the write error and the information used for the recovery from the write error, recovering the write data having the write error; and based on the recovered write data, transmitting a second write request to the memory system. 10. The method of claim 9 , wherein the error occurrence information comprises the physical address of the write data having the write error. 11. The method of claim 10 , further comprising, based on a plurality of pieces of error occurrence information being acquired, determining, by the host, recovery priorities based on physical addresses included in the plurality of pieces of error occurrence information, wherein the acquiring of the write data having the write error and the information used for the recovery from the write error comprises acquiring from the memory system a plurality of pieces of write data having a plurality of write errors, and a plurality of pieces of information used for recoveries from the plurality of write errors, and wherein the recovering of the write data having the write error comprises recovering the plurality of pieces of write data having the plurality of write errors based on the plurality of pieces of information used for the recoveries from the plurality of write errors, according to the recovery priorities. 12. The method of claim 10 , further comprising, based on a plurality of pieces of error occurrence information being acquired, determining, by the host, recovery priorities based on an acquisition order of the plurality of pieces of error occurrence information, wherein the acquiring of the write data having the write error and the information used for the recovery from the write error comprises acquiring from the memory system a plurality of pieces of write data having a plurality of write errors, and a plurality of pieces of information used for recoveries from the plurality of write errors, and wherein the recovering of the write data having the write error comprises recovering the plurality of pieces of write data having the plurality of write errors based on the plurality of pieces of information used for the recoveries from the plurality of write errors, according to the recovery priorities. 13. The method of claim 9 , wherein the information used for the recovery from the write error comprises at least one of an ECC parity of the write data having the write error, a recovery parity, normal data in a recovery unit corresponding to the write error, or management information of the memory system. 14. The method of claim 9 , wherein, based on the write error occurring in a data area, the information used for the recovery from the write error comprises metadata corresponding to the write data having the write error. 15. The method of claim 14 , wherein the recovering of the write data having the write error comprises: based on the metadata, determining whether to recover the write data having the write error by the host; and based on a result the determining, recovering the write data having the write error by the host. 16. The method of claim 15 , wherein the determining whether to recover the write data having the write error comprises determining whether to recover the write data having the write error by using validity information included in the metadata. 17. The method of claim 9 , wherein the acquiring of the write data having the write error and the information used for the recovery from the write error comprises accessing a controller memory buffer (CMB) included in the memory system, or accessing a host memory buffer (HMB) included in the host. 18. The method of claim 9 , wherein the transmitting of the second write request to the memory system comprises determining a new physical address based on mapping information of the memory system, and transmitting the second write request to the memory system based on the new physical address and the recovered write data. 19. A computing system comprising: a memory system comprising a memory device; and a host configured to transmit a write request to the memory system based on write data and a physical address, wherein the memory system, in response to the write request of the host, is configured to: store the write data and the physical address received from the host in a buffer of the memory system, perform a write operation on the memory device based on the write data and the physical address, based on a writ

Assignees

Inventors

Classifications

  • in block erasable memory, e.g. flash memory · CPC title

  • using codes or arrangements adapted for a specific type of error (G06F11/1048 takes precedence) · CPC title

  • using arrangements adapted for a specific error detection or correction feature · CPC title

  • Online error correction · CPC title

  • in relation to data integrity, e.g. data losses, bit errors · CPC title

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What does patent US11288183B2 cover?
A method of operating a memory system including a memory device, including in response to a write request of a host, storing write data and a physical address received from the host in a buffer; performing a write operation on the memory device based on the write data and the physical address; based on a write error corresponding to the write data occurring, asynchronously providing the host wi…
Who is the assignee on this patent?
Samsung Electronics Co Ltd
What technology area does this patent fall under?
Primary CPC classification G06F12/0246. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Mar 29 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 7 related publications on this page (citations in our corpus or others sharing the same primary CPC).