Operation methods of memory system and host, and computing system

Patent metadata

Field	Value
Publication number	US-11157357-B2
Application number	US-202016855000-A
Country	US
Kind code	B2
Filing date	Apr 22, 2020
Priority date	Oct 4, 2019
Publication date	Oct 26, 2021
Grant date	Oct 26, 2021

Abstract

A method of operating a memory system including a memory device, including reading data from the memory device based on a first physical address received from a host according to a read request received from the host; detecting a read error of the read data; correcting the read data based on the detecting; transmitting the corrected data to the host; asynchronously transmitting to the host an error occurrence signal for the read error; generating information about the read error; transmitting the information about the read error to the host; and rewriting the corrected data based on a second physical address received from the host according to a write request of the host.

First claim

What is claimed is:

1. A method of operating a memory system including a memory device, the method comprising:
reading data from the memory device based on a first physical address received from a host according to a read request received from the host;
detecting a read error of the read data;
correcting the read data based on the detecting;
transmitting the corrected data to the host;
asynchronously transmitting to the host an error occurrence signal for the read error;
generating information about the read error, by the memory system;
transmitting the information about the read error to the host; and
rewriting the corrected data based on a second physical address received from the host according to a write request of the host.

2. The method of claim 1 , wherein the information about the read error includes at least one of a physical address, an error type, and a number of error bits of the read data.

3. The method of claim 1 , wherein the information about the read error includes the corrected data.

4. The method of claim 1 , wherein the first physical address is different from the second physical address.

5. A method of operating a host configured to control a memory system, the method comprising:
transmitting a read request from the host to the memory system based on a first physical address;
receiving read data corresponding to the read request from the memory system;
asynchronously receiving an error occurrence signal for a read error corresponding to the read data from the memory system;
receiving information about the read error from the memory system; and
transmitting a recovery command for recovering the read error to the memory system based on the read data and the information about the read error,
wherein the transmitting of the recovery command comprises:
determining a second physical address using the information about the read error; and
transmitting a write request for writing the read data to the second physical address to the memory system,

wherein the transmitting of the recovery command to the memory system further comprises:
retransmitting the read request to the memory system; and
receiving a duplicate copy of the read data from the memory system, and

wherein the write request comprises a request for writing the received duplicate copy of the read data to the second physical address.

6. The method of claim 5 , wherein the information about the read error includes the read data.

7. The method of claim 6 , wherein the write request comprises a request for writing the read data included in the information about the read error to the second physical address.

8. The method of claim 5 , wherein the first physical address is different from the second physical address.

9. The method of claim 5 , wherein the information about the read error includes at least one of a physical address, an error type, and a number of error bits of the read data.

10. The method of claim 5 , further comprising:
receiving information about a plurality of read errors from the memory system; and
determining a priority corresponding to the plurality of read errors based on the information about the plurality of read errors,
wherein the transmitting of the recovery command to the memory system comprises transmitting a plurality of recovery commands for recovering the plurality of read errors to the memory system based on the information about the plurality of read errors according to the determined priority.

11. The method of claim 5 , wherein the information about the read error is received from the memory system based on an information request transmitted to the memory system by the host.

12. The method of claim 11 , wherein the information request is transmitted to the memory system based on a determination by the host that the host is in an idle state.

13. The method of claim 5 , further comprising:
determining, by the host, whether the read data includes at least one of target data of garbage collection for the memory system or invalid data of the memory system; and
transmitting the recovery command to the memory system by the host based on the at least one of the target data of the garbage collection or the invalid data being included in the read data corresponding to the read error.

14. The method of claim 5 , further comprising:
receiving a response signal corresponding to the recovery command from the memory system; and
updating mapping information of the memory system by the host based on the response signal.

15. A computing system comprising:
a memory system including a memory device; and
a host configured to transmit a read request including a first physical address to the memory system,
wherein the memory system, in response to the read request of the host, is configured to:
read data from the memory device based on the first physical address received from the host,
detect a read error of the read data,
correct the read data based on the detecting,
transmit the corrected data to the host,

wherein the memory system is further configured to:
asynchronously transmit an error occurrence signal for the read error to the host,
generate information about the read error, by the memory system, and
transmit the information about the read error to the host, and

wherein, based receiving on the error occurrence signal, the host is configured to transmit a recovery command for recovering the read error to the memory system based on the corrected data and the information about the read error.

16. The computing system of claim 15 , wherein the host is configured to:
determine a second physical address using the information about the read error, and
transmit a write request for writing the corrected data to the second physical address to the memory system.

17. The computing system of claim 15 , wherein the memory system is configured to:
store the information about the read error, and
transmit the information about the read error to the host based on receiving a request for the information about the read error.

18. The computing system of claim 15 , wherein the host is configured to store the information about the read error based on receiving the information about the read error.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Chansol
• Balakrishnan Suman Prakash
• Kim Seokhwan

Classifications

• G06F11/1068 Primary

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title

• G06F3/0619

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G06F11/1012

  using codes or arrangements adapted for a specific type of error (G06F11/1048 takes precedence) · CPC title

• G06F12/10

  Address translation · CPC title

• G06F11/073 Primary

  in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00) · CPC title