Digital pixel having high sensitivity and dynamic range

Patent metadata

Field	Value
Publication number	US-11284025-B2
Application number	US-202016890483-A
Country	US
Kind code	B2
Filing date	Jun 2, 2020
Priority date	Jun 2, 2020
Publication date	Mar 22, 2022
Grant date	Mar 22, 2022

Abstract

A digital pixel includes a capacitive transimpedance amplifier (CTIA) coupled to a photodiode that receives an electrical charge and output an integration voltage. An integration capacitor coupled to the CTIA accumulates the integration voltage over an integration period. A comparator compares the accumulated integration voltage with a threshold voltage and generates a control signal at a first level each time the accumulated integration voltage is greater than the threshold voltage. A charge subtraction circuit receives the control signal at the first level and discharges the accumulated integration voltage each time the control signal at the first level is received from the comparator. An analog or digital counter receives the control signal at the first level and adjusts a counter value each time the control signal is received from the comparator. An output interface communicates the counter value to an image processing circuit at an end of the integration period.

First claim

What is claimed is:

1. A digital pixel comprising:
a photodiode;
a capacitive transimpedance amplifier coupled to the photodiode and arranged to receive an electrical charge generated by the photodiode and output an integration voltage proportional to the electrical charge;
an integration capacitor coupled to the capacitive transimpedance amplifier and configured to accumulate the integration voltage generated by the capacitive transimpedance amplifier over an integration period;
a comparator coupled to the integration capacitor and configured to compare the accumulated integration voltage across the integration capacitor with a threshold voltage and to generate a control signal at a first level each time a determination is made that the accumulated integration voltage across the integration capacitor is greater than the threshold voltage;
a charge subtraction circuit coupled to an output of the comparator and an input of the capacitive transimpedance amplifier, wherein the charge subtraction circuit is arranged to inject an electrical charge at the input of the capacitive transimpedance amplifier that is opposite the electrical charge from the photodiode;
a counter coupled to the comparator and configured to receive the control signal at the first level from the comparator and adjust a counter value each time the control signal at the first level is received from the comparator; and
an output interface arranged to communicate the counter value to an image processing circuit at an end of the integration period.

2. The digital pixel of claim 1 , comprising a residual readout circuit coupled to the integration capacitor and configured to output a residual voltage from the integration capacitor at the end of the integration period.

3. The digital pixel of claim 2 , further comprising an analog to digital converter coupled to the residual readout circuit and configured to output a binary residual value corresponding to the residual voltage from the residual readout circuit.

4. The digital pixel of claim 3 , wherein the output interface is further arranged to communicate the counter value and binary residual value to the image processing circuit at an end of the integration period.

5. The digital pixel of claim 1 , wherein the counter includes an analog counter having a count capacitor and wherein the analog counter is arranged to adjust a fixed portion of charge from the count capacitor each time the analog counter receives the control signal at the first level from the comparator.

6. The digital pixel of claim 1 , wherein the counter includes a reset circuit configured to set the counter value to an initial value at a beginning of the integration period.

7. The digital pixel of claim 1 comprising a charge subtraction circuit coupled to the integration capacitor and to an output of the comparator and configured to receive the control signal at the first level from the comparator and to discharge the accumulated integration voltage, or a portion thereof, on the integration capacitor each time the control signal at the first level is received from the comparator.

8. The digital pixel of claim 1 , wherein the charge subtraction circuit includes a subtraction capacitor and variable voltage input, the variable voltage input being adjustable to set a level of the electrical charge injected at the input of the capacitive transimpedance amplifier that is opposite the electrical charge from the photodiode.

9. The digital pixel of claim 1 , wherein the size of the integration capacitor is less than or equal to about one of 10 pF, 5 pF, 1 pF, 500 fF, 200 fF, 100 fF, 50 fF, 20 fF, 10 fF, 5 fF, 2 fF, 1.5 fF, 1.4 fF, 1 fF, 0.5 fF, and 0.1 fF.

10. A method for operating a digital pixel having a photodiode and an integration capacitor, the method comprising:
generating a first electrical charge in response to an input light signal incident on the photodiode over an integration period;
receiving, by a capacitive transimpedance amplifier, the first electrical charge;
injecting, from a charge subtraction circuit, a second electrical charge at the input of the capacitive transimpedance amplifier that is opposite the first electrical charge from the photodiode;
outputting, from the capacitive transimpedance amplifier, an integration voltage proportional to a sum of the first electrical charge and the second electric charge;
accumulating the integration voltage on the integration capacitor;
comparing the accumulated integration voltage across the integration capacitor with a threshold voltage;
adjusting a counter value each time the voltage across the integration capacitor exceeds the threshold voltage; and
outputting, at an end of the integration period, the counter value to an image processor.

11. The method of claim 10 comprising removing the accumulated integration voltage, or a portion thereof, on the integration capacitor each time the voltage across the integration capacitor exceeds the threshold voltage.

12. The method of claim 10 comprising receiving, at a residual readout circuit, residual voltage from the integration capacitor at the end of the integration period.

13. The method of claim 12 , comprising outputting, by a residual readout circuit, the residual voltage from the integration capacitor at the end of the integration period.

14. The method of claim 13 , further comprising receiving, by an analog to digital converter, the residual voltage and outputting a binary residual value corresponding to the residual voltage from the residual readout circuit.

15. The method of claim 14 comprising communicating the counter value and binary residual value to the image processing circuit at an end of the integration period.

16. The method of claim 10 comprising removing, by a charge subtraction circuit, the accumulated integration voltage on the integration capacitor each time the charge subtraction circuit receives the control signal at the first level from the comparator.

17. An image sensor comprising:
an image processing circuit; and
an array of digital pixels coupled to the image processing circuit, each digital pixel including:
a photodiode;
a capacitive transimpedance amplifier coupled to the photodiode and arranged to receive an electrical charge generated by the photodiode and output a integration voltage proportional to the electrical charge;
an integration capacitor coupled to the capacitive transimpedance amplifier and configured to accumulate the integration voltage generated by the capacitive transimpedance amplifier over an integration period;
a comparator coupled to the integration capacitor and configured to compare the accumulated integration voltage across the integration capacitor with a threshold voltage and to generate a control signal at a first level each time a determination is made that the accumulated integration voltage across the integration capacitor is greater than the threshold voltage;
a charge subtraction circuit coupled to an output of the comparator and an input of the capacitive transimpedance amplifier, wherein the charge subtraction circuit is arranged to inject an electrical charge at the input of the capacitive transimpedance amplifier that is opposite the electrical charge from the photodiode;
a counter coupled to the comparator and configured to receive the control signal at the first level from the comparator and adjust a counter value each time the control signal at the first level is received from the comparator; and
an output interface arranged to communicate the counter value to an image processing circuit at an end of the integ

Assignees

• Raytheon Co

Inventors

• Malone Neil R
• Harris Micky
• Kennedy Adam M
• Paloczi George
• Vampola John L
• Boemler Christian M

Classifications

• H04N25/771

  comprising storage means other than floating diffusion · CPC title

• H04N25/59 Primary

  by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance · CPC title

• H04N25/571

  involving a non-linear response · CPC title

• H04N25/772 Primary

  comprising A/D, V/T, V/F, I/T or I/F converters · CPC title

• H04N25/77

  Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components · CPC title