Digital unit cell with analog counter element

Patent metadata

Field	Value
Publication number	US-9854192-B2
Application number	US-201615096572-A
Country	US
Kind code	B2
Filing date	Apr 12, 2016
Priority date	Apr 12, 2016
Publication date	Dec 26, 2017
Grant date	Dec 26, 2017

Abstract

According to one aspect, embodiments herein provide a digital unit cell comprising a photodiode, an integration capacitor, a comparator configured to compare a voltage across the integration capacitor with a threshold voltage and to generate a control signal at a first level each time the voltage across the integration capacitor is greater than the threshold voltage, a charge subtraction circuit configured to receive the control signal at the first level and to discharge accumulated charge on the integration capacitor each time the control signal at the first level is received, at least one analog counter configured to receive the control signal at the first level from the comparator and to decrease a count voltage by a fixed amount each time the control signal at the first level is received from the comparator, and a counter readout circuit configured to provide the count voltage to an image processing circuit.

First claim

What is claimed is:

1. A digital unit cell comprising:
a photodiode;
an integration capacitor coupled to the photodiode and configured to accumulate charge generated by the photodiode responsive to an input light signal incident on the photodiode over an integration period;
a comparator coupled to the integration capacitor and configured to compare a voltage across the integration capacitor with a threshold voltage and to generate a control signal at a first level each time a determination is made that the voltage across the integration capacitor is greater than the threshold voltage;
a charge subtraction circuit coupled to the integration capacitor and to the comparator and configured to receive the control signal at the first level from the comparator and to discharge the accumulated charge on the integration capacitor each time the control signal at the first level is received from the comparator;
at least one analog counter coupled to the comparator and configured to receive the control signal at the first level from the comparator and to decrease a count voltage by a fixed amount each time the control signal at the first level is received from the comparator; and
a counter readout circuit coupled to the at least one analog counter and configured to provide the count voltage to an image processing circuit at an end of the integration period.

2. The digital unit cell of claim 1 , wherein the at least one analog counter comprises a count capacitor coupled to the counter readout circuit and configured to maintain the count voltage.

3. The digital unit cell of claim 2 , wherein the at least one analog counter further comprises a transistor circuit coupled to the count capacitor and configured to remove a fixed portion of charge from the count capacitor each time the at least one analog counter receives the control signal at the first level from the comparator.

4. The digital unit cell of claim 3 , wherein the at least analog counter further comprises a reset circuit coupled to the count capacitor and configured to set the count voltage to an initial value at a beginning of the integration period.

5. The digital unit cell of claim 3 , further comprising a sample and hold capacitor coupled to the integration capacitor and configured to receive a residual voltage from the integration capacitor at the end of the integration period.

6. The digital unit cell of claim 5 , further comprising a residual readout circuit coupled to the sample and hold capacitor and configured to output the residual voltage from the sample and hold capacitor at the end of the integration period.

7. The digital unit cell of claim 6 , further comprising an image processing circuit coupled to the counter readout circuit and the residual readout circuit and configured to receive the count voltage from the counter readout circuit, receive the residual voltage from the residual readout circuit, and calculate a total charge accumulated by the digital unit cell based on the count voltage and the residual voltage.

8. The digital unit cell of claim 7 , wherein the image processing circuit is further configured to calculate the total charge accumulated by the digital unit cell by:
calculating, based at least on the count voltage, a total number of times that the charge subtraction circuit discharged the accumulated charge on the integration capacitor; and
calculating the total charge accumulated by the digital unit cell by multiplying the total number of times that the charge subtraction circuit discharged the accumulated charge on the integration capacitor by the fixed portion of charge and adding the residual voltage.

9. The digital unit cell of claim 1 , wherein the charge subtraction circuit comprises a transistor circuit configured to remove the accumulated charge on the integration capacitor each time the charge subtraction circuit receives the control signal at the first level from the comparator.

10. The digital unit cell of claim 1 , wherein the at least one analog counter includes a first analog counter selectively coupled to the counter readout circuit via a first counter selection switch and a second analog counter selectively coupled to the counter readout circuit via a second counter selection switch.

11. A method for operating a digital unit cell comprising a photodiode and an integration capacitor, the method comprising:
generating charge in response to an input light signal incident on the photodiode over an integration period;
accumulating the charge on the integration capacitor;
comparing a voltage across the integration capacitor with a threshold voltage;
removing the accumulated charge on the integration capacitor each time the voltage across the integration capacitor exceeds the threshold voltage;
decreasing, by a fixed amount, a count voltage of an analog counter each time the voltage across the integration capacitor exceeds the threshold voltage; and
reading out, at an end of the integration period, the count voltage of the analog counter to an image processor.

12. The method of claim 11 , wherein removing the accumulated charge on the integration capacitor includes coupling the integration capacitor to ground.

13. The method of claim 11 , wherein decreasing, by the fixed amount, the count voltage of the analog counter includes removing a fixed portion of charge from a count capacitor in the analog counter.

14. The method of claim 13 , further comprising setting, at a beginning of the integration period, the count voltage of the analog counter to an initial value.

15. The method of claim 13 , further comprising reading out, at an end of the integration period, a residual voltage across the integration capacitor to the image processor.

16. The method of claim 15 , further comprising calculating, with the image processor, a total charge accumulated by the digital unit cell based on the count voltage and the residual voltage.

17. The method of claim 16 , wherein calculating a total charge accumulated by the digital unit cell includes:
calculating, based at least on the count voltage, a total number of times that the accumulated charge on the integration capacitor was discharged; and
calculating the total charge accumulated by the digital unit cell by multiplying the total number of times that the accumulated charge on the integration capacitor was discharged by the fixed portion of charge and adding the residual voltage.

18. An image sensor comprising:
an image processing circuit;
an array of unit cells coupled to the image processing circuit, each unit cell comprising:
a photodiode coupled to an integration capacitor, the integration capacitor configured to accumulate charge generated by an input light signal incident on the photodiode over an integration period;
a comparator coupled to the integration capacitor and configured to compare a voltage across the integration capacitor with a threshold voltage and generate a control signal at a first level each time a determination is made that the voltage across the integration capacitor is greater than the threshold voltage;
a charge subtraction circuit coupled to the integration capacitor and the comparator and configured to discharge the accumulated charge on the integration capacitor each time the control signal at the first level is received from the comparator;
means for maintaining a count voltage of an analog counter, the count voltage corresponding to a number of times the accumulated charge on the integration capacitor has been discharged; and
a readout circuit coupled to the analog counter and configu

Assignees

• Raytheon Co

Inventors

• Boemler Christian M

Classifications

• H04N25/709 Primary

  Circuitry for control of the power supply · CPC title

• G01J1/44 Primary

  Electric circuits {(for command of an exposure part G03B7/02)} · CPC title

• H04N5/378

  Electricity · mapped topic

• H04N5/3698 Primary

  Electricity · mapped topic

• H04N25/78

  Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters · CPC title