Deskewing method for a physical layer interface on a multi-chip module

Patent metadata

Field	Value
Publication number	US-11283589-B2
Application number	US-202017128720-A
Country	US
Kind code	B2
Filing date	Dec 21, 2020
Priority date	Apr 29, 2019
Publication date	Mar 22, 2022
Grant date	Mar 22, 2022

Abstract

Systems, apparatuses, and methods for implementing a deskewing method for a physical layer interface on a multi-chip module are disclosed. A circuit connected to a plurality of communication lanes trains each lane to synchronize a local clock of the lane with a corresponding global clock at a beginning of a timing window. Next, the circuit symbol rotates each lane by a single step responsive to determining that all of the plurality of lanes have an incorrect symbol alignment. Responsive to determining that some but not all of the plurality of lanes have a correct symbol alignment, the circuit symbol rotates lanes which have an incorrect symbol alignment by a single step. When the end of the timing window has been reached, the circuit symbol rotates lanes which have a correct symbol alignment and adjusts a phase of a corresponding global clock to compensate for missed symbol rotations.

First claim

What is claimed is:

1. A circuit comprising:
first circuitry configured to synchronize a local clock of each of a plurality of communication lanes with a global clock;
second circuitry configured to:
symbol rotate each lane of the plurality of lanes that has an incorrect alignment, responsive to a determination that one or more of the plurality of communication lanes have an incorrect symbol alignment; and
check symbol timing of each of the plurality of lanes, responsive to detecting the end of a timing window.

2. The circuit as recited in claim 1 , wherein responsive to detecting the end of the timing window, the circuit is configured to symbol rotate each lane of the plurality of lanes that has a correct symbol alignment.

3. The circuit as recited in claim 1 , wherein to synchronize the local clock of each of the plurality of communication lanes with the global clock, the first circuitry is configured to sweep the local clock across multiple phases while sampling the local clock with the global clock.

4. The circuit as recited in claim 1 , wherein the first circuitry is configured to determine the local clock is aligned with the global clock responsive to detection of an edge transition during the sweep of the local clock.

5. The circuit as recited in claim 4 , wherein subsequent to the local clock being aligned with the global clock, a phase of the local clock is adjusted to meet setup and hold timing requirements.

6. The circuit as recited in claim 1 , wherein subsequent to the local clock being synchronized with the global clock, the circuit is configured to sample data on a communication lane of the plurality of communication lanes with the local clock.

7. The circuit as recited in claim 1 , wherein data sampled on a communication lane with the local clock is conveyed to a deserializer.

8. A method comprising:
synchronizing a local clock of each of a plurality of communication lanes with a global clock;
symbol rotating each lane of the plurality of lanes, responsive to a determination that none of the plurality of communication lanes have a correct symbol alignment; and
checking symbol timing of each of the plurality of lanes, responsive to detecting the end of a timing window.

9. The method as recited in claim 8 , wherein responsive to detecting the end of the timing window, the method comprises symbol rotating each lane of the plurality of lanes that has a correct symbol alignment.

10. The method as recited in claim 8 , wherein to synchronize the local clock of each of the plurality of communication lanes with the global clock, the method comprises sweeping the local clock across multiple phases while sampling the local clock with the global clock.

11. The method as recited in claim 8 , further comprising determining the local clock is aligned with the global clock responsive to detection of an edge transition during the sweep of the local clock.

12. The method as recited in claim 11 , wherein subsequent to the local clock being aligned with the global clock, the method comprises adjusting a phase of the local clock to meet setup and hold timing requirements.

13. The method as recited in claim 8 , wherein subsequent to the local clock being synchronized with the global clock, the method comprises sampling data on a communication lane of the plurality of communication lanes with the local clock.

14. The method as recited in claim 8 , further comprises conveying data sampled on a communication lane with the local clock is conveyed to a deserializer.

15. A system comprising:
a first functional unit;
a channel with a plurality of communication lanes; and
a second functional unit coupled to the first functional unit via the channel, wherein the second functional unit is configured to convey a first global clock and a first data signal to the first functional unit via the channel;
wherein the first functional unit is configured to:
synchronize a local clock of each of a plurality of communication lanes with the global clock;
symbol rotate each lane of the plurality of lanes that has an incorrect alignment, responsive to a determination that one or more of the plurality of communication lanes have an incorrect symbol alignment; and
check symbol timing of each of the plurality of lanes, responsive to detecting the end of a timing window.

16. The system as recited in claim 15 , wherein responsive to detecting the end of the timing window, the first functional unit is configured to symbol rotate each lane of the plurality of lanes that has a correct symbol alignment.

17. The system as recited in claim 15 , wherein to synchronize the local clock of each of the plurality of communication lanes with the global clock, the first functional unit is configured to sweep the local clock across multiple phases while sampling the local clock with the global clock.

18. The system as recited in claim 15 , wherein the first functional unit is configured to determine the local clock is aligned with the global clock responsive to detection of an edge transition during the sweep of the local clock.

19. The system as recited in claim 18 , wherein subsequent to the local clock being aligned with the global clock, a phase of the local clock is adjusted to meet setup and hold timing requirements.

20. The system as recited in claim 15 , wherein subsequent to the local clock being synchronized with the global clock, the first functional unit is configured to sample data on a communication lane of the plurality of communication lanes with the local clock.

Assignees

• Advanced Micro Devices Inc
• Ati Technologies Ulc

Inventors

• Gupta Varun
• Paraschou Milam
• Talbot Gerald R
• Dollin Gurunath
• Tohidi Damon
• Carpenter Eric Ian
• Gallun Chad S
• Cooper Jeffrey
• Cho Hanwoo
• Likens Iii Thomas H
• Dow Scott F
• Tresidder Michael J

Classifications

• H04L25/14 Primary

  Channel dividing arrangements {, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver} · CPC title

• H04L7/0337 Primary

  Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals · CPC title

• H04L7/0008

  Synchronisation information channels, e.g. clock distribution lines · CPC title

• H04L7/04 Primary

  Speed or phase control by synchronisation signals {(H04L7/0075 takes precedence)} · CPC title