Calibration of a time-to-digital converter using a virtual phase-locked loop

Patent metadata

Field	Value
Publication number	US-11283459-B1
Application number	US-202117217695-A
Country	US
Kind code	B1
Filing date	Mar 30, 2021
Priority date	Mar 30, 2021
Publication date	Mar 22, 2022
Grant date	Mar 22, 2022

Abstract

In at least one embodiment, a method includes generating a digital time code corresponding to an input clock signal using a time-to-digital converter responsive to a reference clock signal and a time-to-digital converter calibration signal. The method includes generating the time-to-digital converter calibration signal based on the digital time code. Generating the time-to-digital converter calibration signal includes generating a digital error signal based on the digital time code and an estimated digital time code, and adapting the time-to-digital converter calibration signal based on the digital error signal.

First claim

What is claimed is:

1. A method for generating a clock signal, the method comprising:
generating a digital time code corresponding to an input clock signal using a time-to-digital converter responsive to a reference clock signal and a time-to-digital converter calibration signal;
generating a digital error signal based on the digital time code and an estimated digital time code; and
generating the time-to-digital converter calibration signal based on the digital error signal and the digital time code.

2. The method as recited in claim 1 wherein the time-to-digital converter comprises a coarse time-to-digital converter and a fine time-to-digital converter, and generating the digital time code comprises:
generating a coarse time code and a residue signal based on the input clock signal and the reference clock signal;
generating a fine time code based on the residue signal;
applying the time-to-digital converter calibration signal as a digital gain adjustment to the fine time code to generate an adjusted fine time code; and
combining the coarse time code and the adjusted fine time code to generate the digital time code.

3. The method as recited in claim 1 wherein generating the digital error signal comprises:
computing a difference between the digital time code and the estimated digital time code to generate the digital error signal;
generating an integrated error signal based on the digital error signal;
generating a proportional error signal based on the digital error signal;
computing a sum of the integrated error signal and the proportional error signal;
integrating the sum to generate an integrated sum;
generating an expected digital time code; and
generating the estimated digital time code based on the sum of the expected digital time code and the integrated sum.

4. The method as recited in claim 1 wherein generating the digital error signal comprises compensating for rollover error caused by using less than all bits of the digital time code to generate the digital error signal.

5. The method as recited in claim 1 wherein the digital error signal has zero mean.

6. The method as recited in claim 1 wherein the estimated digital time code is generated with the same period as the digital time code.

7. The method as recited in claim 1 further comprising generating an output clock signal based on the digital time code and a feedback digital time code.

8. A clock generator comprising:
a time-to-digital converter configured to generate a digital time code based on an input clock signal, a reference clock signal, and a time-to-digital converter calibration signal; and
a calibration circuit configured to generate the time-to-digital converter calibration signal based on the digital time code, the calibration circuit including a phase-locked loop configured to generate a digital phase error signal based on the digital time code, an estimated digital time code, and the input clock signal, and including an adaptive loop configured to generate the time-to-digital converter calibration signal based on the digital phase error signal and a fine time code of the digital time code.

9. The clock generator as recited in claim 8 wherein the time-to-digital converter comprises:
a coarse time-to-digital converter configured to generate a coarse time code and a residue signal based on the input clock signal and the reference clock signal;
a fine time-to-digital converter configured to generate the fine time code based on the residue signal and to apply the time-to-digital converter calibration signal as a digital gain adjustment to the fine time code to generate an adjusted fine time code; and
a combiner configured to combine the coarse time code and the adjusted fine time code to generate the digital time code.

10. The clock generator as recited in claim 8 wherein the phase-locked loop includes two integrators and is configured to cause the digital phase error signal to have zero mean.

11. The clock generator as recited in claim 8 wherein the phase-locked loop comprises an integrator programmed with a free-running period estimate to generate the estimated digital time code with the same period as the digital time code.

12. The clock generator as recited in claim 8 wherein the estimated digital time code is a spur-attenuated version of the digital time code.

13. The clock generator as recited in claim 8 wherein the phase-locked loop further comprises a wrap detection and correction circuit configured to compensate for rollover error caused by using less than all bits of the digital time code by the phase-locked loop and the adaptive loop.

14. The clock generator as recited in claim 8 wherein the digital phase error signal is a difference between the estimated digital time code and the digital time code.

15. The clock generator as recited in claim 8 wherein the adaptive loop includes a least mean squares filter.

16. The clock generator as recited in claim 8 wherein the phase-locked loop comprises:
a digital circuit configured to compute a difference between the digital time code and the estimated digital time code to generate the digital phase error signal;
a first integrator configured to generate an integrated phase error signal based on the digital phase error signal;
a proportional circuit path configured to generate a proportional phase error signal based on the digital phase error signal;
a second digital circuit configured to compute a sum of the integrated phase error signal and the proportional phase error signal;
a second integrator responsive to the sum;
a free running period estimator circuit configured to generate an expected digital time code; and
a third digital circuit configured to generate the estimated digital time code based on the sum of the expected digital time code and an output of the second integrator.

17. The clock generator as recited in claim 8 further comprising a digital phase-locked loop configured to generate an output time signal based on the digital time code and a feedback digital time code.

18. A method for estimating an integral nonlinearity (INL) of an analog-to-digital converter including a coarse analog-to-digital converter and a fine analog-to digital converter, the method comprising:
generating a digital time code including a fine time code and corresponding to an input clock signal using a time-to-digital converter responsive to a reference clock signal and a time-to-digital converter calibration signal; and
for each value of the fine time code, generating an error signal based on the digital time code, the fine time code, and an estimated value of the digital time code and averaging the error signal over multiple clock cycles to generate an average error signal.

19. The method as recited in claim 18 further comprising determining a maximum average error signal based on the average error signal generated for each value of the fine time code.

20. The method, as recited in claim 18 , wherein the time-to-digital converter comprises a coarse time-to-digital converter and a fine time-to-digital converter, and generating the digital time code comprises:
generating a coarse time code and a residue signal based on the input clock signal and the reference clock signal;
generating the fine time code based on the residue signal;
applying the time-to-digital converter calibration signal as a digital gain adjustment to the fine time code to generate an adjusted fine time code; and
combining the coarse time code and the adjusted fine time code to generat

Assignees

• Skyworks Solutions Inc

Inventors

• Monk Timothy Adam
• Pastorello Douglas F
• Balakrishnan Krishnan
• Ranganathan Raghunandan Kolar

Classifications

• H03L7/23

  with pulse counters or frequency dividers · CPC title

• H03L7/0992

  comprising a counter or a frequency divider · CPC title

• H03L7/087

  using at least two phase detectors or a frequency and phase detector in the loop · CPC title

• H03L7/085

  concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00) · CPC title

• G04F10/005

  Time-to-digital converters [TDC] (analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60) · CPC title