Programmable neuron core with on-chip learning and stochastic time step control

Patent metadata

Field	Value
Publication number	US-11281963-B2
Application number	US-201615276111-A
Country	US
Kind code	B2
Filing date	Sep 26, 2016
Priority date	Sep 26, 2016
Publication date	Mar 22, 2022
Grant date	Mar 22, 2022

Abstract

An integrated circuit (IC), as a computation block of a neuromorphic system, includes a time step controller to activate a time step update signal for performing a time-multiplexed selection of a group of neuromorphic states to update. The IC includes a first circuitry to, responsive to detecting the time step update signal for a selected group of neuromorphic states: generate an outgoing data signal in response to determining that a first membrane potential of the selected group of neuromorphic states exceeds a threshold value, wherein the outgoing data signal includes an identifier that identifies the selected group of neuromorphic states and a memory address (wherein the memory address corresponds to a location in a memory block associated with the integrated circuit), and update a state of the selected group of neuromorphic states in response to generation of the outgoing data signal.

First claim

What is claimed is:

1. An integrated circuit comprising:
a time step controller to randomly activate a time step update signal for performing a randomly time-multiplexed selection of a group of neuromorphic states to update;
a time-step-activated circuitry coupled to the time step controller and to, responsive to detecting the time step update signal for a selected group of neuromorphic states:
generate an outgoing data signal in response to determining that a first membrane potential of the selected group of neuromorphic states exceeds a threshold value, wherein the outgoing data signal includes an identifier that identifies the selected group of neuromorphic states and a memory address that identifies a location in a memory block associated with the integrated circuit, and
update a state of the selected group of neuromorphic states in response to generation of the outgoing data signal; and

a signal-activated circuitry coupled to the time step controller and to, responsive to the time step update signal not being activated and to receipt of an incoming data signal corresponding to a second group of neuromorphic states:
add a weight value of the incoming data signal to a second membrane potential of the second group of neuromorphic states, to generate an updated second membrane potential, and
store the updated second membrane potential to a register set, wherein the signal- activated circuitry is separate from the time-step-activated circuitry.

2. The integrated circuit of claim 1 , further comprising the register set to store the selected group of neuromorphic states and the second group of neuromorphic states, wherein the signal-activated circuitry is further to:
identify, within the register set, a register storing the second group of neuromorphic states corresponding to a second identifier retrieved from the incoming data signal; and
retrieve the second membrane potential from the register set, wherein the register set comprises a first register set to store a first subset of the group of second neuromorphic states accessed by the signal-activated circuitry, and a second register set to store a second subset of the group of second neuromorphic states that are also accessed by the time-step-activated circuitry.

3. The integrated circuit of claim 1 , wherein the signal-activated circuitry further comprises a learning unit to perform a learning operation by updating the weight value for the second group of neuromorphic states, to generate an updated weight value, and wherein the signal-activated circuitry is further to transmit the updated weight value through a router, the updated weight value to be stored in the memory block.

4. The integrated circuit of claim 3 , wherein a state of the group of second neuromorphic states is reflected by a learning counter, and the time-step-activated circuitry is further to:
set the learning counter to a maximum counter value upon generation of an outgoing data signal for the second group of neuromorphic states:
decrement the learning counter responsive to each time step update signal; and
wherein the learning counter is further to trigger selection of a weight update value that is added to or subtracted from the weight value, to generate the updated weight value.

5. The integrated circuit of claim 1 , wherein a state of the group of second neuromorphic states is reflected by a refractory period counter, and the time-step-activated circuitry is further to:
set the refractory period counter to a maximum counter value upon generation of an outgoing data signal for the second group of neuromorphic states; and
decrement the refractory period counter responsive to each time step update signal, wherein the time-step-activated circuitry is to block generation of a subsequent outgoing data signal and the signal-activated circuitry is to block adding a weight value of a subsequent incoming data signal until the refractory period counter reaches zero.

6. The integrated circuit of claim 1 , wherein the time-step-activated circuitry is further to:
multiply the first membrane potential of the selected group of neuromorphic states with a leak factor to generate a first updated membrane potential; and
responsive to the first membrane potential being less than the threshold value, replace the first membrane potential with the first updated membrane potential.

7. The integrated circuit of claim 6 , wherein the time-step-activated circuitry is further to:
compare an input data value of the selected group of neuromorphic states with a pseudo- randomly-generated input signal threshold; and
responsive to the input data value being greater than the pseudo-randomly-generated input signal threshold, add the input data value to the first updated membrane potential before replacing the first membrane potential with the first updated membrane potential.

8. The integrated circuit of claim 6 , wherein the time-step-activated circuitry is further to:
compare a bias value for the selected group of neuromorphic states with a pseudo- randomly-generated input bias threshold; and
responsive to the bias value being greater than the pseudo-randomly-generated input bias threshold, add the bias value to the first updated membrane potential before replacing the first membrane potential with the first updated membrane potential.

9. A system comprising:
a memory block;
a computation block; and
a router coupled to the memory block and to the computation block,
wherein the computation block comprises:
a time step controller to randomly activate a time step update signal for performing a randomly time-multiplexed selection of a group of neuromorphic states to update;
a time-step-activated circuitry coupled to the time step controller and to, responsive to detecting the time step update signal for a selected group of neuromorphic states:
generate an outgoing data signal in response to determining that a first membrane potential of the selected group of neuromorphic states exceeds a threshold value, wherein the outgoing data signal includes an identifier that identifies the selected group of neuromorphic states and a memory address, wherein the memory address corresponds to a location in the memory block, and
update a state of the selected group of neuromorphic states in response to generation of the outgoing data signal; and

a learning unit coupled to the time step controller and to, responsive to detecting no time step update signal and to receipt of an incoming data signal, perform a learning operation by:
identifying a second group of neuromorphic states corresponding to an identifier retrieved from the incoming data signal, and
updating a weight value of the incoming data signal, to generate an updated weight value to be provided to the router, for storage at a second memory address of the memory block, wherein the learning unit is separate from the time-step-activated circuitry.

10. The system of claim 9 , further comprising a register set to store the selected group of neuromorphic states and the second group of neuromorphic states, wherein the computation block further comprises a signal-activated circuitry to, responsive to receipt of the incoming data signal:
identify a register, within the register set, for the second group of neuromorphic states;
retrieve, from the register, a second membrane potential for the second group of neuromorphic states;
add the weight value of the incoming data signal to the second membrane potential of the second group of neuromorphic states, to generate an updated second membrane potential; and
store the updated second membrane potential back to the register set.

11. The system of claim 10 , wherein the register set

Assignees

• Intel Corp

Inventors

• Kumar Raghavan
• Chen Gregory K
• Sumbul Huseyin Ekin
• Knag Phil

Classifications

• G06N3/049 Primary

  Temporal neural networks, e.g. delay elements, oscillating neurons or pulsed inputs · CPC title

• G06N3/063

  using electronic means · CPC title

• G06N3/088

  Non-supervised learning, e.g. competitive learning · CPC title